EP910PI-15T vs EP910PI-20 Vergleich

Detaillierter Direktvergleich von EP910PI-15T von Altera und EP910PI-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PI-15T EP910PI-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,95 $9,75
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD (EP910 series) —
Macrocells 24 24
Dedicated Inputs 12 12
I/O Pins 24 —
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) —
Versorgungsspannung 4.5 V to 5.5 V (5 V nominal) —
Propagation Delay (tPD) 15 ns max (speed grade -15) 20 ns
Technology CMOS EEPROM (electrically erasable) CMOS EPROM (UV-erasable windowed variants available)
Gehäuse 40-pin PDIP (Plastic DIP, R-PDIP-T40) PDIP-40 (PI suffix)
Montageart Through-Hole Through-Hole
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] —
Betriebstemperatur [DATA_NEEDED: industrial/commercial temp range] -40C to +85C (industrial)
Programming JEDEC-standard, serial/parallel programmer —
RoHS-Status [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] unknown
Device Family — Altera Classic EPLD Family
Supply Voltage (VCC) — 5 V (+/- 5%)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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