EP910PI-15T vs EP910PI-20 比較
詳細な並列比較: EP910PI-15T メーカー: Altera および EP910PI-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-15T | EP910PI-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.95 | $9.75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| 電源電圧 | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 20 ns |
| Technology | CMOS EEPROM (electrically erasable) | CMOS EPROM (UV-erasable windowed variants available) |
| パッケージ | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (PI suffix) |
| 実装タイプ | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| 動作温度 | [DATA_NEEDED: industrial/commercial temp range] | -40C to +85C (industrial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS ステータス | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | unknown |
| Device Family | — | Altera Classic EPLD Family |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |