EP910PI-15T vs EP910PI-20 比較
詳細並排比較 EP910PI-15T 由 Altera 與 EP910PI-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-15T | EP910PI-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| 供應電壓 | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 20 ns |
| Technology | CMOS EEPROM (electrically erasable) | CMOS EPROM (UV-erasable windowed variants available) |
| 封裝 | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (PI suffix) |
| 安裝類型 | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| 工作溫度 | [DATA_NEEDED: industrial/commercial temp range] | -40C to +85C (industrial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | unknown |
| Device Family | — | Altera Classic EPLD Family |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |