EP910PI-40 vs EP910PC-30 Vergleich

Detaillierter Direktvergleich von EP910PI-40 von Altera und EP910PC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP910PI-40 EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP910PI-40 EP910PC-30
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,85 $6,50
Device Family Classic EPLD —
Part Number EP910PI-40 —
Architecture PAL-type macrocell, CMOS, UV-erasable —
Number of Macrocells 24 —
Number of Dedicated Inputs 12 —
Number of I/O Lines 24 —
External Clock Inputs 2 —
Maximale Taktfrequenz 25 MHz —
Propagation Delay (tPD) 43 ns —
Speed Grade -40 (43 ns) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V ±10%
Gehäuse PDIP-40 (Plastic DIP, 40-pin) PDIP-40 (plastic DIP, 0.6 inch)
Betriebstemperatur 0C to +70C (commercial) 0C to +70C (commercial)
Montageart Through-Hole Through-hole DIP
Process Technology CMOS (UV-erasable) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] Non-compliant (contains lead, PDIP package)
Programming Method UV-erase + Altera programmer (legacy) —
Programmable Polarity Yes (user-configurable output) —
Output Enable Control Yes (per-pin three-state) —
Family — Altera Classic EPLD
Macrocells — 24
Usable Gates — ~450
Pin-to-Pin Propagation Delay (tPD) — 30 ns
Maximum Counter Frequency (fCNT) — 33.3 MHz
Logic Inputs — 36 dedicated
I/O Pins — 12 bidirectional
Logic Array Blocks (LABs) — 4
Programming Technology — UV-erasable EPROM cell
TTL Emulation — 100% TTL-compatible
Power Dissipation — [DATA_NEEDED: power dissipation mW]

Datenblätter & Ressourcen

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