EP910PI-40 vs EP910PC-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-40 sa pamamagitan ng Altera at EP910PC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-40 EP910PC-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Device Family Classic EPLD —
Part Number EP910PI-40 —
Architecture PAL-type macrocell, CMOS, UV-erasable —
Number of Macrocells 24 —
Number of Dedicated Inputs 12 —
Number of I/O Lines 24 —
External Clock Inputs 2 —
Maksimum na Taktiko ng Oras 25 MHz —
Propagation Delay (tPD) 43 ns —
Speed Grade -40 (43 ns) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V ±10%
Packhaging PDIP-40 (Plastic DIP, 40-pin) PDIP-40 (plastic DIP, 0.6 inch)
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Uri ng Pagpapasok Through-Hole Through-hole DIP
Process Technology CMOS (UV-erasable) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Non-compliant (contains lead, PDIP package)
Programming Method UV-erase + Altera programmer (legacy) —
Programmable Polarity Yes (user-configurable output) —
Output Enable Control Yes (per-pin three-state) —
Family — Altera Classic EPLD
Macrocells — 24
Usable Gates — ~450
Pin-to-Pin Propagation Delay (tPD) — 30 ns
Maximum Counter Frequency (fCNT) — 33.3 MHz
Logic Inputs — 36 dedicated
I/O Pins — 12 bidirectional
Logic Array Blocks (LABs) — 4
Programming Technology — UV-erasable EPROM cell
TTL Emulation — 100% TTL-compatible
Power Dissipation — [DATA_NEEDED: power dissipation mW]

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