EPM5192AGC84-20 vs EPM5192AJI84-20 Vergleich
Detaillierter Direktvergleich von EPM5192AGC84-20 von Altera und EPM5192AJI84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AGC84-20 | EPM5192AJI84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $41,20 | $10,95 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Gehäuse | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | WQCCJ (JEDEC) |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Commercial | Industrial |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] |
| Montageart | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Device Family | — | MAX 5000 (EPM5192) |
| Logic Cells / Macrocells | — | 192 macrocells |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Propagation Delay (tPD) | — | 33 ns |
| Maximum Frequency (fCNT) | — | 66.7 MHz |
| Supply Voltage (VCC) | — | 5 V nominal (4.5 V to 5.5 V) |
| Package Type | — | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) |
| Terminal Form | — | J-Bend |
| Number of Terminals | — | 84 |
| Programmability | — | UV-erasable window + OTP |
| Pin-Anzahl | — | 84 |
| Lebenszyklusstatus | — | Obsolete (legacy Altera MAX 5000) |