EPM5192AGC84-20 vs EPM5192AJI84-20 对比
详细并排对比 EPM5192AGC84-20 出自 Altera 和 EPM5192AJI84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192AGC84-20 | EPM5192AJI84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $41.20 | $10.95 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| 封装 | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | WQCCJ (JEDEC) |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Commercial | Industrial |
| 电源电压 | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] |
| 安装类型 | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Device Family | — | MAX 5000 (EPM5192) |
| Logic Cells / Macrocells | — | 192 macrocells |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Propagation Delay (tPD) | — | 33 ns |
| Maximum Frequency (fCNT) | — | 66.7 MHz |
| Supply Voltage (VCC) | — | 5 V nominal (4.5 V to 5.5 V) |
| Package Type | — | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) |
| Terminal Form | — | J-Bend |
| Number of Terminals | — | 84 |
| Programmability | — | UV-erasable window + OTP |
| 引脚数量 | — | 84 |
| 生命周期状态 | — | Obsolete (legacy Altera MAX 5000) |