EPM5192AGC84-20 vs EPM5192AJI84-20 비교
다음의 상세 나란히 비교: EPM5192AGC84-20 제조: Altera 및 EPM5192AJI84-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192AGC84-20 | EPM5192AJI84-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $41.20 | $10.95 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| 패키지 | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | WQCCJ (JEDEC) |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Commercial | Industrial |
| 공급 전압 | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] |
| 실장 유형 | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Device Family | — | MAX 5000 (EPM5192) |
| Logic Cells / Macrocells | — | 192 macrocells |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Propagation Delay (tPD) | — | 33 ns |
| Maximum Frequency (fCNT) | — | 66.7 MHz |
| Supply Voltage (VCC) | — | 5 V nominal (4.5 V to 5.5 V) |
| Package Type | — | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) |
| Terminal Form | — | J-Bend |
| Number of Terminals | — | 84 |
| Programmability | — | UV-erasable window + OTP |
| 핀 수 | — | 84 |
| 수명 주기 상태 | — | Obsolete (legacy Altera MAX 5000) |