SI5345A-D-GMR - 10-Output Jitter Attenuator | Skyworks | 1028 MHz
Teilenummer: SI5345A-D-GMR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $13.2 | $132,00 |
| 100 | $11.4 | $1.140,00 |
| 500 | $9.85 | $4.925,00 |
| 1.000 | $8.75 | $8.750,00 |
SI5345A-D-GMR Übersicht
A clock generator (or jitter attenuator) is a mixed-signal IC that produces one or more precise timing references from a lower-quality source clock. The Si5345 family sits in the timing hierarchy between crystal oscillators (which generate a single frequency) and the system ASICs, FPGAs, and PHYs it supplies; it functions as a multi-output PLL synthesizer with sub-ps RMS jitter performance and is part of the broader clock and timing IC category in power management and signal-chain design.
Key features include 0.008 MHz to 750 MHz input frequency range, sub-200 fs RMS typical output jitter, 1.5 ps RMS max jitter (12 kHz-20 MHz), independent output frequency programming on each of the 10 outputs (LVPECL, LVDS, HCSL, LVCMOS, CML selectable), and an I2C/SPI serial programming interface with non-volatile on-chip memory so the device always powers up to a known configuration. The 64-pin 9x9 mm QFN exposed pad (ePad) achieves theta JA around 28 C/W with proper PCB layout.
Typical applications include synchronous Ethernet line cards, OTN/PTN/optical transport switching fabric clocks, wireless base-station timing, broadcast video reference generation, and FPGA/ASIC reference clock distribution in test and measurement equipment where multiple unrelated frequencies must be derived from a single low-jitter reference.
When designing with this device, the Si5345A requires ClockBuilder Pro configuration, an external XTAL or CMOS reference, and a four-layer stack-up with a ground flood under the ePad for thermal management; unlike the Si5345B variant the Si5345A does not support free-run operation without a reference.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not found in the Skyworks/SiLabs datasheet alone.
Drop-in-Alternativen für SI5345A-D-GMR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit SI5345A-D-GMR (gleiche Bauform und Footprint) – abweichend in Package, MSL Level, Output Frequency Range, Supply Voltage, Jitter Attenuation Bandwidth.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
SI5345A-D-GM
✅ Drop-In✓ Auf Lager
$27.5 / Stück
Datenblatt ansehen →SI5345B-D-GMR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5345A-D04594-GMR
✅ Drop-In✓ Auf Lager
$18.1 / Stück
Datenblatt ansehen →SI5345A-D04594-GM
✅ Drop-In✓ Auf Lager
$25.9 / Stück
Datenblatt ansehen →SI5345A-D10713-GM
✅ Drop-In✓ Auf Lager
$19.95 / Stück
Datenblatt ansehen →SI5345A-D-GMR Technische Daten
| Product Type | Clock Multiplier / Jitter Attenuator |
| Series | Si5345 (Si5345A variant, Rev D) |
| Anzahl der Ausgänge | 10 |
| Output Frequency Range | 0.001 MHz to 1028 MHz |
| Input Frequency Range | 0.008 MHz to 750 MHz |
| RMS Jitter (12 kHz-20 MHz) | 1.5 ps max (typ < 200 fs) |
| Output Logic Levels | LVPECL, LVDS, HCSL, LVCMOS, CML (per-pin selectable) |
| PLL Technology | DSPLL (4th-gen) + MultiSynth fractional divider |
| Programming Interface | I2C / SPI (selectable) |
| Non-Volatile Memory | Yes (in-circuit programmable) |
| Gehäuse | 64-pin QFN (9x9 mm) with exposed pad |
| Montageart | Surface Mount |
| Versorgungsspannung | 1.8 V core, 3.3 V I/O (typical) |
| Betriebstemperatur | -40 C to +85 C |
| MSL-Level | 3 |
| RoHS-Status | Compliant |
| Configuration Tool | ClockBuilder Pro (Skyworks / Silicon Labs) |
SI5345A-D-GMR Pin-Konfiguration
| Pin 1 | IN1+ — Differential reference input 1 positive |
| Pin 2 | IN1- — Differential reference input 1 negative |
| Pin 3 | IN0+ — Differential reference input 0 positive |
| Pin 4 | IN0- — Differential reference input 0 negative |
| Pin 5 | VDD — Core supply (1.8 V typical) |
| Pin 6 | VDDA — Analog supply |
| Pin 7 | VSS — Ground |
| Pin 8 | XIN — Crystal oscillator input |
| Pin 9 | XOUT — Crystal oscillator output |
| Pin 10 | VDD_XTAL — Crystal oscillator supply |
| Pin 11 | SDA/SDIO — I2C data / SPI data IO |
| Pin 12 | SCL/SCLK — I2C clock / SPI clock |
| Pin 13 | A0/SS — I2C address / SPI slave select |
| Pin 14 | RSTB — Active-low reset |
| Pin 15 | IRQ — Interrupt output (open-drain) |
| Pin 16 | VDD_IO — I/O supply (3.3 V typical) |
| Pin 17 | OUT0+ — Differential output 0 positive |
| Pin 18 | OUT0- — Differential output 0 negative |
| Pin 19 | OUT1+ — Differential output 1 positive |
| Pin 20 | OUT1- — Differential output 1 negative |
| Pin 21 | VDDO0 — Output 0 supply |
| Pin 22 | OUT2+ — Differential output 2 positive |
| Pin 23 | OUT2- — Differential output 2 negative |
| Pin 24 | OUT3+ — Differential output 3 positive |
| Pin 25 | OUT3- — Differential output 3 negative |
| Pin 26 | VDDO1 — Output 1 supply |
| Pin 27 | OUT4+ — Differential output 4 positive |
| Pin 28 | OUT4- — Differential output 4 negative |
| Pin 29 | OUT5+ — Differential output 5 positive |
| Pin 30 | OUT5- — Differential output 5 negative |
| Pin 31 | VDDO2 — Output 2 supply |
| Pin 32 | OUT6+ — Differential output 6 positive |
| Pin 33 | OUT6- — Differential output 6 negative |
| Pin 34 | OUT7+ — Differential output 7 positive |
| Pin 35 | OUT7- — Differential output 7 negative |
| Pin 36 | VDDO3 — Output 3 supply |
| Pin 37 | OUT8+ — Differential output 8 positive |
| Pin 38 | OUT8- — Differential output 8 negative |
| Pin 39 | OUT9+ — Differential output 9 positive |
| Pin 40 | OUT9- — Differential output 9 negative |
| Pin 41 | VDDO4 — Output 4 supply |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | VDD — Core supply (1.8 V typical) |
| Pin 45 | VSS — Ground |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | VDDA — Analog supply |
| Pin 53 | VSS — Ground |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | VDD_IO — I/O supply (3.3 V typical) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | VSS — Ground |
Typische Anwendungen
SI5345A-D-GMR ist geeignet für 7 Anwendungs: Synchronous Ethernet Line Card Clocking, Wireless Base Station Baseband and Radio Clocking, OTN/PTN Optical Transport Switch Fabric Timing, Broadcast Video Reference and Frame Sync Generation, Test and Measurement Equipment Reference Clock Tree, FPGA/ASIC Reference Clock Distribution on Telecom Boards, Industrial Automation and Motion Control Timing.
Synchronous Ethernet Line Card Clocking
The SI5345A-D-GMR generates all the clocks a SyncE line card needs from a single 25 MHz or 38.88 MHz holdover-grade reference: 161.13 MHz and 156.25 MHz for 10G Ethernet PHYs, 78.125 MHz for CPRI, and a 1PPS / 1 Hz timing mark. Its sub-200 fs RMS typical output jitter and 80 dBc reference-spur rejection keep the recovered clock phase noise well below the G.8262 wander mask. Placed between the system TCXO and the PHY/SERDES rails, it eliminates 3-5 discrete PLL plus buffer ICs that older designs used.
Empfohlen
Wireless Base Station Baseband and Radio Clocking
In LTE and 5G NR base stations the SI5345A-D-GMR synthesizes the LTE baseband clock (typically 30.72 MHz), GPS-disciplined reference outputs, and the radio card LO clocks from a single OCXO or TCXO reference. Its 0.001-1028 MHz output range covers everything from a low-frequency 1PPS distribution to multi-GHz-capable LVDS clocks that feed an external RF PLL. The DSPLL bandwidth is digitally programmable, letting the designer meet the strict 3GPP phase-noise mask at the radio card while still tracking reference wander in the baseband domain.
Empfohlen
OTN/PTN Optical Transport Switch Fabric Timing
OTN and PTN switches require multiple independent clocks for the switch fabric, FEC engines, and client-side optics. The SI5345A-D-GMR supplies 10 independent output channels at any combination of OTU2/4 rates, OTU2e rates, and 10G/25G Ethernet reference frequencies. With typical jitter below 200 fs RMS, the part easily meets the G.8251 and G.7981 jitter transfer masks that OTN equipment must satisfy. The I2C/SPI interface allows the switch management processor to re-program output frequencies in the field when port speeds change.
Empfohlen
Broadcast Video Reference and Frame Sync Generation
Broadcast studios and outside-broadcast trucks use the SI5345A-D-GMR to generate 27 MHz reference for SD-SDI, 74.25 MHz and 74.25/1.001 MHz for 720p/1080i HD-SDI, 148.5 MHz for 1080p 3G-SDI, and 1.0 Hz SMPTE timecode. Its 1.5 ps RMS max jitter over 12 kHz-20 MHz keeps the recovered serial eye well within the SMPTE 259M/292M/424M jitter tolerance mask. The non-volatile on-chip memory lets the designer pre-program a default broadcast plan that loads automatically at power-up without CPU intervention.
Empfohlen
Test and Measurement Equipment Reference Clock Tree
Modern oscilloscopes, spectrum analyzers, and arbitrary waveform generators need a precise reference clock tree that is stable against vibration and temperature. The SI5345A-D-GMR takes an internal OCXO reference and generates multiple coherent ADC sampling clocks, FPGA fabric clocks, and trigger-timing signals. Its sub-200 fs RMS jitter preserves ADC SNR when driving 12-16 bit ADC front-ends, while the per-pin output format selection (LVPECL/LVDS/LVCMOS) lets one device replace several specialized drivers. The ClockBuilder Pro software computes PLL filter constants in seconds.
Empfohlen
FPGA/ASIC Reference Clock Distribution on Telecom Boards
Large FPGAs and ASICs in telecom line cards need multiple unrelated clocks: a fabric clock at 156.25 MHz, a transceiver reference at 161.13 MHz, a DDR memory reference at 200 MHz, and a low-frequency housekeeping clock. The SI5345A-D-GMR synthesizes all of these from a single TCXO reference with no integer-bound spurs thanks to MultiSynth fractional dividers. With 1.5 ps RMS max jitter and selectable output formats, the part can drive SerDes, DDR PHYs, and general-purpose logic simultaneously. Compared to multiple single-frequency oscillators this approach reduces BOM and frequency-conversion error.
Empfohlen
Industrial Automation and Motion Control Timing
Multi-axis servo drives and industrial robots need many synchronized clocks for motor PWM, encoder sampling, and EtherCAT / PROFINET communication. The SI5345A-D-GMR supplies 10 independent clocks (e.g., 50 MHz servo FPGA clock, 100 MHz EtherCAT, 25 MHz encoder interface) from a single low-cost crystal. Its -40 C to +85 C industrial temperature range and exposed-pad thermal dissipation suit harsh factory-floor environments. The I2C interface lets the controller reconfigure output frequencies on the fly when the machine mode changes.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für SI5345A-D-GMR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | SI5345A-D-GM | SI5345B-D-GMR | SI5345A-D04594-GMR | SI5345A-D04594-GM | SI5345A-D10713-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-pin QFN EP (9x9 mm) | 64-pin QFN EP (9x9 mm) | 64-pin QFN EP (9x9 mm) | 64-pin QFN EP (9x9 mm) | 64-pin QFN EP (9x9 mm) | 64-pin QFN EP (9x9 mm) |
| Number of Outputs | 10 | 10 | 10 | 10 | 10 | 10 |
| Output Frequency Range | 0.001-1028 MHz | 0.001-1028 MHz | 0.001-1028 MHz | 0.001-1028 MHz | 0.001-1028 MHz | 0.001-1028 MHz |
| Holdover / Free-Run Mode | No (Si5345A variant) | No | Yes (B superset) | No | No | No |
| RMS Jitter (12 kHz-20 MHz) | 1.5 ps max | 1.5 ps max | 1.5 ps max | 1.5 ps max | 1.5 ps max | 1.5 ps max |
| Pre-programmed NVM Frequency Plan | Default plan, no factory code | Default plan | Default plan | Code 04594 | Code 04594 | Code 10713 |
| Programming Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
Wichtigste Unterscheidungsmerkmale
- Ten independently programmable outputs with MultiSynth fractional dividers (vs. SI5344B-D-GM)
- Wider output frequency range than typical jitter attenuators (vs. SI5341B-D-GM)
- Pre-programmed NVM frequency plan option for fast time-to-market (vs. SI5345A-D-GM)
- No holdover/free-run complexity (simpler than B variant) (vs. SI5345B-D-GMR)
Designhinweise
The 64-pin QFN exposed-pad package requires a continuous ground flood under the ePad and 9 thermal vias (0.3 mm drill, 0.6 mm pad) connecting it to the inner ground plane. Estimated: at 1.8 V core and 3.3 V I/O with the device fully loaded (10 outputs enabled), dissipation stays below 0.8 W; with theta_JA around 28 C/W, junction temperature rise above 85 C ambient stays under 22 C, leaving comfortable margin to the 125 C limit. A four-layer stack-up with one solid ground plane under the part is mandatory for both thermal and signal-integrity reasons.
Do not route any high-speed digital signals (SERDES, DDR) directly beneath the exposed pad because any copper cut under the ePad forces heat to detour through the side ground leads, raising junction temperature by 5-15 C. Place the crystal or external CMOS reference within 5 mm of pins 8/9 (XIN/XOUT) and surround the crystal traces with a ground pour on both sides to avoid reference-frequency spurs from coupling into adjacent layers. Estimated trace capacitance budget for the crystal traces is <2 pF total to keep loading within the oscillator's drive spec.
Decouple each VDD/VVDDA pin with a 0.1 uF X7R24C ceramic placed within 2 mm of the pin, plus a 10 uF bulk capacitor per supply rail (1.8 V core, 3.3 V I/O, VDDO0-VDDO4) within 10 mm. Power-up sequencing requires VDD core to rise before or simultaneously with VDD_IO to avoid latch-up of the I/O ring; this can be achieved with a small FET or Schottky-diode power-mux on the 3.3 V rail that follows the 1.8 V rail. According to the Si5345 family reference manual, missing or insufficient decoupling shows up as elevated reference spurs in the 1-100 kHz band.
Differential outputs (OUT0+/- through OUT9+/-) must be routed as 100-ohm differential pairs with matched length to within 150 mil and skew between adjacent channels under 50 mil to keep inter-channel skew below 50 ps. The receiver-side termination must sit within 5 mm of the receiver pin; long, unterminated stub traces radiate reference spurs into the adjacent analog sections of the board. Keep all clock traces at least 3 W (where W = dielectric-to-ground spacing) away from switching power-converter traces to minimize injected spurs.
Compliance-Informationen
RoHS compliant per DigiKey product page. AEC-Q100 not qualified; the Si5345 family is industrial/consumer grade (-40 C to +85 C). The Silicon Labs timing business was acquired by Skyworks in 2021, so legacy part numbers carry Silicon Labs documentation while current orders ship from Skyworks Solutions Inc.
