EPF8636AQC160-3 - FLEX 8000 FPGA, 6K Gates, 504 Cells | Intel
Référence : EPF8636AQC160-3 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1 385,00 |
| 500 | $11.4 | $5 700,00 |
| 1 000 | $9.95 | $9 950,00 |
EPF8636AQC160-3 Présentation
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs or LABs) connected by programmable interconnect and surrounded by programmable I/O cells. FPGAs sit hierarchically between CPLDs and ASICs: they offer higher logic density than CPLDs, and unlike ASICs they can be re-programmed multiple times after PCB assembly. The FLEX 8000 family was Altera's first look-up-table (LUT)-based SRAM FPGA architecture, replacing the company's earlier MAX-era EPROM logic and bridging the gap toward modern Cyclone and Stratix device families.
Key features of the EPF8636AQC160-3 include 4,992 bits of embedded SRAM, JTAG-based IEEE 1149.1 boundary-scan support, multiVolt I/O for interfacing with 3.3 V and 5 V devices, and a commercial 0 °C to +70 °C operating temperature range. The device is configured via a serial configuration EPROM or the built-in JTAG port, allowing field upgrades of firmware/HDL bitstreams. Its 160-pin PQFP footprint was the FLEX 8000 family's highest-density package option and is pin-compatible with other EPF8636AQC160-speed-grade variants.
Typical applications include telecommunications line-card glue logic, industrial PLC and motor-control peripheral interfaces, ISA/PCI bus bridges in legacy systems, and replacement of multiple 74-series TTL/MSI devices with a single re-programmable part. The wide I/O count (118) and 5 V tolerance make the EPF8636AQC160-3 especially well suited as a bridge between microprocessors and parallel peripherals in long-life-cycle embedded platforms. This part is now marked Obsolete (EOL) by Intel and is generally stocked through legacy distributors for maintenance of installed industrial and telecom systems.
When designing with this FPGA, ensure that the JTAG chain includes the correct TCK frequency for the configuration EPROM and that unused I/O pins are configured as inputs with internal pull-ups to minimise power and EMI. Plan for the 5 V VCCIO rail separately from any 3.3 V logic on the board. This page consolidates distributor pricing, drop-in compatible speed-grade variants, and design notes specifically for engineers maintaining legacy FLEX 8000 designs not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour EPF8636AQC160-3 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPF8636AQC160-3 (même facteur de forme et même empreinte) — différant par Package, Configuration Method, Usable Gates, Operating Temperature, Process Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPF8636AQC160-4
✅ Remplacement direct✓ En stock
$198 / unité
Voir la fiche technique →EPF8636AQC160-2
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPF8636AQC160-3N
✅ Remplacement direct✓ En stock
$29.25 / unité
Voir la fiche technique →EPF8452AQC160-3
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$13.85 / unité
Voir la fiche technique →EPF8636AQC160-3 Valeurs maximales et caractéristiques électriques
| Family | FLEX 8000 |
| Usable Gates | 6,000 |
| Logic Cells / Elements | 504 |
| Logic Array Blocks (LABs) | 63 |
| User I/Os | 118 |
| Embedded SRAM | 4,992 bits |
| Maximum Frequency | 125 MHz |
| Process Technology | 0.42 µm CMOS |
| Tension d'alimentation | 5 V (4.75 V to 5.25 V) |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) |
| Boîtier | 160-pin PQFP / BQFP (28 × 28 mm) |
| Type de montage | Surface Mount (Gull-Wing) |
| Configuration Method | SRAM, JTAG (IEEE 1149.1) / Serial EPROM |
| Boundary-Scan Support | Yes (JTAG) |
Configuration des broches de EPF8636AQC160-3
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | I/O — User I/O pin (bank 1) |
| Broche 5 | I/O — User I/O pin (bank 1) |
| Broche 6 | I/O — User I/O pin (bank 1) |
| Broche 7 | I/O — User I/O pin (bank 1) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | I/O — User I/O pin (bank 1) |
| Broche 11 | I/O — User I/O pin (bank 1) |
| Broche 12 | I/O — User I/O pin (bank 1) |
| Broche 13 | I/O — User I/O pin (bank 1) |
| Broche 14 | I/O — User I/O pin (bank 1) |
| Broche 15 | GND — Ground |
| Broche 16 | I/O — User I/O pin (bank 1) |
| Broche 17 | I/O — User I/O pin (bank 1) |
| Broche 18 | I/O — User I/O pin (bank 1) |
| Broche 19 | I/O — User I/O pin (bank 1) |
| Broche 20 | I/O — User I/O pin (bank 1) |
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| Broche 38 | I/O — User I/O pin (bank 1) |
| Broche 39 | I/O — User I/O pin (bank 1) |
| Broche 40 | I/O — User I/O pin (bank 1) |
| Broche 41 | VCCINT — Core supply 5 V |
| Broche 42 | I/O — User I/O pin (bank 2) |
| Broche 43 | I/O — User I/O pin (bank 2) |
| Broche 44 | I/O — User I/O pin (bank 2) |
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| Broche 52 | I/O — User I/O pin (bank 2) |
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| Broche 57 | I/O — User I/O pin (bank 2) |
| Broche 58 | I/O — User I/O pin (bank 2) |
| Broche 59 | I/O — User I/O pin (bank 2) |
| Broche 60 | GND — Ground |
| Broche 61 | I/O — User I/O pin (bank 2) |
| Broche 62 | I/O — User I/O pin (bank 2) |
| Broche 63 | I/O — User I/O pin (bank 2) |
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| Broche 79 | I/O — User I/O pin (bank 2) |
| Broche 80 | I/O — User I/O pin (bank 2) |
| Broche 81 | I/O — User I/O pin (bank 3) |
| Broche 82 | VCCIO — I/O supply 5 V (or 3.3 V with multiVolt) |
| Broche 83 | I/O — User I/O pin (bank 3) |
| Broche 84 | I/O — User I/O pin (bank 3) |
| Broche 85 | I/O — User I/O pin (bank 3) |
| Broche 86 | I/O — User I/O pin (bank 3) |
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| Broche 97 | I/O — User I/O pin (bank 3) |
| Broche 98 | I/O — User I/O pin (bank 3) |
| Broche 99 | I/O — User I/O pin (bank 3) |
| Broche 100 | GND — Ground |
| Broche 101 | I/O — User I/O pin (bank 3) |
| Broche 102 | I/O — User I/O pin (bank 3) |
| Broche 103 | I/O — User I/O pin (bank 3) |
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| Broche 115 | I/O — User I/O pin (bank 3) |
| Broche 116 | I/O — User I/O pin (bank 3) |
| Broche 117 | I/O — User I/O pin (bank 3) |
| Broche 118 | I/O — User I/O pin (bank 3) |
| Broche 119 | I/O — User I/O pin (bank 4) |
| Broche 120 | VCCINT — Core supply 5 V |
| Broche 121 | I/O — User I/O pin (bank 4) |
| Broche 122 | I/O — User I/O pin (bank 4) |
| Broche 123 | I/O — User I/O pin (bank 4) |
| Broche 124 | I/O — User I/O pin (bank 4) |
| Broche 125 | I/O — User I/O pin (bank 4) |
| Broche 126 | I/O — User I/O pin (bank 4) |
| Broche 127 | I/O — User I/O pin (bank 4) |
| Broche 128 | I/O — User I/O pin (bank 4) |
| Broche 129 | I/O — User I/O pin (bank 4) |
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| Broche 135 | I/O — User I/O pin (bank 4) |
| Broche 136 | I/O — User I/O pin (bank 4) |
| Broche 137 | I/O — User I/O pin (bank 4) |
| Broche 138 | I/O — User I/O pin (bank 4) |
| Broche 139 | GND — Ground |
| Broche 140 | I/O — User I/O pin (bank 4) |
| Broche 141 | I/O — User I/O pin (bank 4) |
| Broche 142 | I/O — User I/O pin (bank 4) |
| Broche 143 | I/O — User I/O pin (bank 4) |
| Broche 144 | I/O — User I/O pin (bank 4) |
| Broche 145 | I/O — User I/O pin (bank 4) |
| Broche 146 | I/O — User I/O pin (bank 4) |
| Broche 147 | I/O — User I/O pin (bank 4) |
| Broche 148 | I/O — User I/O pin (bank 4) |
| Broche 149 | I/O — User I/O pin (bank 4) |
| Broche 150 | I/O — User I/O pin (bank 4) |
| Broche 151 | I/O — User I/O pin (bank 4) |
| Broche 152 | I/O — User I/O pin (bank 4) |
| Broche 153 | I/O — User I/O pin (bank 4) |
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| Broche 155 | I/O — User I/O pin (bank 4) |
| Broche 156 | I/O — User I/O pin (bank 4) |
| Broche 157 | I/O — User I/O pin (bank 4) |
| Broche 158 | I/O — User I/O pin (bank 4) |
| Broche 159 | I/O — User I/O pin (bank 4) |
| Broche 160 | TDI — JTAG Test Data In (dedicated) |
Applications typiques
EPF8636AQC160-3 convient pour 6 applications: Telecom Line-Card Glue Logic, Industrial PLC Peripheral Interface, Legacy ISA / PCI Bus Bridges, TTL/MSI Replacement in Long-Life Systems, Motor Control State Machines, Test & Measurement Front-Ends.
Telecom Line-Card Glue Logic
The EPF8636AQC160-3 fits telecom line-card glue logic because its 118 user I/Os and 5 V tolerance let it sit directly between an E1/T1 framer, a network processor, and parallel peripheral buses. With 504 logic cells across 63 LABs, it can host the state machines, FIFO flags, and interrupt arbiters that tie together an otherwise heterogeneous backplane, while its 125 MHz toggle frequency is more than adequate for low-speed serial aggregation. Replacing four to six discrete 74FCT and 74ABT packages with one FLEX 8000 device reduces board area and simplifies ECO-driven updates via JTAG. Designers should still validate I/O timing against the framer's hold/settle window.
Recommandé
Industrial PLC Peripheral Interface
PLC and motor-control peripherals benefit from the EPF8636AQC160-3's wide I/O count, 5 V tolerance, and commercial 0-70 °C range. It can host encoder-capture logic, PWM generators, and isolated fieldbus-to-backplane bridges in a single re-programmable part, replacing racks of discrete MSI glue. The 4,992 bits of embedded SRAM are sufficient for short frame buffers and status FIFOs, while JTAG reconfigurability lets field technicians update logic between machine variants without changing hardware. Its 160-pin PQFP footprint remains supported in through-hole and socketed adapter boards for legacy PLC chassis.
Recommandé
Legacy ISA / PCI Bus Bridges
The EPF8636AQC160-3 is well matched to legacy ISA and PCI bus bridge designs in industrial PCs and test equipment, where its 5 V I/O and 118 available user pins can directly connect to bus transceivers and address/data demultiplexers. With 504 logic cells it comfortably fits a 32-bit address decoder, byte-enable logic, wait-state generator, and interrupt steering. Its 125 MHz fabric easily accommodates the 8-33 MHz PCI clock domain through conventional clock-domain crossing. In-circuit reconfigurability via JTAG also lets bridge firmware be patched in the field after silicon revisions on either side of the bridge.
Recommandé
TTL/MSI Replacement in Long-Life Systems
Many long-life defence, aviation, and industrial-automation systems still use racks of 74LS/74FCT glue logic. The EPF8636AQC160-3 can absorb dozens of such functions into one re-programmable package, with its 504 cells typically replacing 20-60 equivalent MSI packages. The 160-pin PQFP fits the same board area as a bank of SOIC-20 glue chips, freeing PCB real-estate and reducing assembly cost. JTAG reconfigurability lets one board variant support multiple SKUs by loading different bitstreams, dramatically simplifying spare-parts logistics for installed bases that must remain serviceable for decades.
Recommandé
Motor Control State Machines
Stepper and BLDC motor control often needs tightly-coupled state machines for commutation, fault handling, and encoder feedback - exactly the kind of register-rich logic at which the FLEX 8000 family excels. The EPF8636AQC160-3's 63 LABs provide enough register density to host six-step trapezoidal commutation, PID loops in distributed arithmetic, and quadrature decoders simultaneously. Its 5 V I/O directly drives many industrial opto-isolators and gate drivers, removing level-shift stages from the BOM. Engineers should still verify that propagation delay through the FPGA fabric plus I/O toggling fits within the commutation window for high-RPM applications.
Recommandé
Test & Measurement Front-Ends
Bench instruments and ATE fixtures built in the late 1990s and early 2000s often use the EPF8636AQC160-3 as a programmable I/O expander, scan controller, or custom waveform generator. Its 4,992 bits of SRAM provide enough storage for short stimulus patterns, while 118 user I/Os support parallel stimulus/response buses. JTAG reconfigurability lets the same hardware be reused for new DUTs simply by loading a new bitstream, reducing the cost-per-test of long-lived ATE platforms. Maintaining these instruments now typically relies on legacy stock of the EPF8636AQC160-3 or its drop-in -4 sibling.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPF8636AQC160-3 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPF8636AQC160-4 | EPF8636AQC160-3N | EPF8636AQC160-2 | EPF8452AQC160-3 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 160-pin PQFP (28x28 mm) | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same |
| Usable Gates | 6,000 | 6,000 (same die) | 6,000 (same die) | 6,000 (same die) | 4,000 (lower-density die) |
| Logic Cells | 504 | 504 | 504 | 504 | 336 (-33%) |
| User I/Os | 118 | 118 | 118 | 118 | 120 |
| Speed Grade | -3 (125 MHz) | -4 (faster, ~150 MHz) | -3N (lead-free, same speed) | -2 (slower) | -3 (125 MHz) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
Principaux différenciateurs
- Higher usable-gate density within the FLEX 8000 PQFP-160 family (vs EPF8452AQC160-3)
- Faster speed grade when substituted with EPF8636AQC160-4 (vs EPF8636AQC160-4)
- Lead-free / RoHS-compatible pin-compatible variant (vs EPF8636AQC160-3N)
Notes de conception
The EPF8636AQC160-3 requires a single 5 V supply with the VCCINT (core) and VCCIO (I/O) rails decoupled separately - typically a 100 µF bulk capacitor near the package plus 0.1 µF ceramic caps at every supply pin. With all 118 I/Os toggling at 25 MHz the device can draw up to ~500 mA; ensure the 5 V regulator has at least 1 A headroom and that the PCB power pour is sized accordingly.
The 160-pin PQFP at 0.65 mm pitch requires a 4-layer PCB with 0.5 oz copper pours stitched under the device to dissipate heat and provide low-impedance ground returns. Place all decoupling caps on the same side as the FPGA within 5 mm of their respective supply pins. Length-match CLK and global signal traces to within ±2 mm to avoid skew on the FLEX 8000 fast-row interconnect.
Estimated: at 5 V VCC and 118 I/Os toggling simultaneously, dynamic I/O current can approach 300 mA. Plan decoupling accordingly. Do not drive the JTAG TDI pin with a 3.3 V driver unless a level shifter is added - the EPF8636AQC160-3's JTAG inputs are 5 V TTL-compatible. Always terminate unused I/Os as inputs with weak pull-ups via the Quartus / MAX+PLUS II assignment to prevent shoot-through current during configuration.
Informations de conformité
The standard EPF8636AQC160-3 is an older Altera FLEX 8000 part introduced before RoHS requirements were widely enforced; lead-free compatibility is provided by the -3N suffix variant (EPF8636AQC160-3N). REACH / AEC-Q100 / halogen-free status not specified in the provided web data and marked [DATA_NEEDED] / unknown.
