EPF8636AQC160-3N - FLEX 8000 FPGA, 6K Gates, 504 Cells | Intel
MPN: EPF8636AQC160-3N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $40.5 | $405.00 |
| 100 | $36 | $3,600.00 |
| 500 | $32.4 | $16,200.00 |
| 1,000 | $29.25 | $29,250.00 |
Drop-in alternatives for EPF8636AQC160-3N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPF8636AQC160-3
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View Datasheet βEPF8452AQC160-4
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View Datasheet βEPF8452AQC160-4N
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View Datasheet βEPF8636AQC160-3N Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Device | EPF8636 |
| Usable Gates | 6,000 (16,000 maximum) |
| Logic Elements (LEs) | 504 |
| User I/Os | 118 |
| Embedded Array Blocks (EABs) | 12 |
| Maximum Internal Frequency | 125 MHz |
| Process Technology | 0.42 Β΅m CMOS SRAM |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage (VCCIO) | 5 V |
| Package | 160-pin PQFP / BQFP |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) |
| Speed Grade | -3 (commercial, 125 MHz) |
| Configuration Method | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| RoHS Status | unknown |
| Lead-Free / Halogen-Free | unknown |
| Mounting Type | Surface Mount |
EPF8636AQC160-3N Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | VCCINT β Core supply voltage (5 V) |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | VCCIO β I/O supply voltage (5 V) |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | VCCINT β Core supply voltage (5 V) |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | VCCIO β I/O supply voltage (5 V) |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | VCCINT β Core supply voltage (5 V) |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | VCCIO β I/O supply voltage (5 V) |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | VCCINT β Core supply voltage (5 V) |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | VCCIO β I/O supply voltage (5 V) |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | VCCINT β Core supply voltage (5 V) |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | VCCIO β I/O supply voltage (5 V) |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | VCCINT β Core supply voltage (5 V) |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | GND β Ground |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | VCCIO β I/O supply voltage (5 V) |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | VCCINT β Core supply voltage (5 V) |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | GND β Ground |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | VCCIO β I/O supply voltage (5 V) |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | VCCINT β Core supply voltage (5 V) |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | GND β Ground |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | VCCIO β I/O supply voltage (5 V) |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8636AQC160-3N is suitable for 6 applications: Telecom Interface Glue Logic, Industrial Control State Machines, Peripheral Bus Bridges (PCI / VME / ISA), Legacy 5 V Embedded Systems, Test and Measurement Backplanes, Aerospace and Defense Retrofit Programs.
Telecom Interface Glue Logic
The EPF8636AQC160-3N is well suited for telecom interface glue logic where 5 V tolerant I/O and 118 user pins allow direct connection to legacy TTL/CMOS peripherals. The 504 LEs and 12 EABs provide enough capacity to implement UART multiplexing, HDLC framing, and T1/E1 line-interface state machines in a single device. Designers place it between an MPC860 PowerQUICC or similar 5 V communications controller and external PHY devices. The 125 MHz internal FMAX in speed grade -3 comfortably handles 8 Mbps HDLC data paths and 155 Mbps ATM cell-processing glue. Unlike modern 3.3 V FPGAs, no external level shifters are needed on the I/O bank when interfacing to legacy 5 V peripherals.
Recommended
Industrial Control State Machines
The EPF8636AQC160-3N suits industrial PLC backplanes and motor-control state machines because of its 0-70 Β°C commercial operating range, 5 V supply tolerance, and 504 LEs. Engineers implement ladder-logic replacement, PWM generation, encoder decoding, and Modbus / Profibus protocol bridging on a single chip. The 12 EABs can be configured as dual-port RAM to buffer encoder pulse trains or quadrature samples. Its 160-pin PQFP package is well established on through-hole and reflow production lines still used in industrial OEM factories, where 5 V rails are the norm. Compared to a CPLD of similar I/O count, the FLEX 8000 architecture provides several times more sequential logic capacity for multi-axis motion controllers.
Recommended
Peripheral Bus Bridges (PCI / VME / ISA)
The EPF8636AQC160-3N is widely used as a 5 V peripheral bus bridge, converting between PCI, VME, ISA, and proprietary 32-bit backplanes. Its 118 user I/Os handle the full 32-bit data bus plus 32-bit address bus with control signals in a single device. The 504 LEs absorb the address-decoding, wait-state generation, and bus-arbiter logic; the 12 EABs implement FIFO buffers for write-posting and read-prefetching. With speed grade -3 supporting 125 MHz internal frequency, the bridge operates comfortably at 33 MHz PCI without wait-state insertion. Compared to discrete 74-series glue logic, the FPGA replaces dozens of SSI/MSI packages and enables late-stage bus-protocol fixes via in-circuit reconfiguration.
Recommended
Legacy 5 V Embedded Systems
The EPF8636AQC160-3N is the natural choice for legacy 5 V-only embedded platforms where modern low-voltage FPGAs (Cyclone, Lattice ECP5, Xilinx Spartan-6) are not pin-compatible and cannot operate without level shifters. Common targets include VMEbus single-board computers, CompactPCI carrier cards, and 5 V custom backplanes from the 1990s and early 2000s. The 6K usable gates and 504 LEs deliver ample capacity for custom I/O controllers, interrupt aggregators, and watchdog timers. Because the FLEX 8000 architecture supports in-circuit reconfigurability, firmware updates are possible without removing the board from service - a key advantage in deployed fielded systems where downtime is expensive.
Recommended
Test and Measurement Backplanes
The EPF8636AQC160-3N finds application in legacy test and measurement equipment where it implements timing generators, pattern sequencers, and instrument-interface bridges. Its 504 LEs and 12 EABs provide the logic density required for IEEE-488 (GPIB) controllers, VXI register interfaces, and parallel ATE pin-electronics drivers. The 5 V-tolerant 118 I/Os are well matched to the TTL-level pin electronics used in test heads from the late 1990s. Designers appreciate the FLEX 8000 family's deterministic timing model, which simplifies the static timing analysis required for ATE applications. Compared to a discrete TTL implementation, the FPGA reduces board area by 60-70% and simplifies design changes during equipment development.
Recommended
Aerospace and Defense Retrofit Programs
The EPF8636AQC160-3N is found in aerospace and defense retrofit programs that extend the service life of fielded avionics, radar signal processors, and naval electronics originally designed with FLEX 8000 logic. Because the part is no longer in production, sourcing through franchised distributors with full traceability documentation is essential for these programs. The 504 LEs and 6K usable gates handle MIL-STD-1553 bus monitors, ARINC 429 interfaces, and radar timing generators. Some retrofit programs have moved to modern plastic-packaged equivalents of the same FLEX 8000 die, preserving the original bitstream and avoiding costly re-verification. The 0-70 Β°C commercial temperature range is acceptable for many sheltered avionics bays and shipboard equipment enclosures.
Recommended
Recommended Products Summary
Engineering reference data for EPF8636AQC160-3N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8636AQC160-3 | EPF8636AQC160-4N | EPF8452AQC160-3 | EPF8452AQC160-4 | EPF8452AQC160-4N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 160-pin PQFP | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 4,000 (-33%) | 4,000 (-33%) | 4,000 (-33%) |
| Logic Elements | 504 | 504 | 504 | 336 (-33%) | 336 (-33%) | 336 (-33%) |
| Speed Grade / Max Frequency | -3 / 125 MHz | -3 / 125 MHz | -4 / ~150 MHz | -3 / 125 MHz | -4 / ~150 MHz | -4 / ~150 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| User I/Os | 118 | 118 | 118 | 118 | 118 | 118 |
| Process Technology | 0.42 Β΅m CMOS SRAM | 0.42 Β΅m CMOS SRAM | 0.42 Β΅m CMOS SRAM | 0.42 Β΅m CMOS SRAM | 0.42 Β΅m CMOS SRAM | 0.42 Β΅m CMOS SRAM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Higher logic density than EPF8452AQC160-3 in identical 160-pin PQFP (vs EPF8452AQC160-3)
- Lower-cost commercial speed grade than EPF8636AQC160-4N (vs EPF8636AQC160-4N)
- Standard lead-free 'N' suffix for RoHS-aligned assembly (vs EPF8636AQC160-3)
Design Notes
The EPF8636AQC160-3N requires a stable 5 V Β±5% supply on both VCCINT and VCCIO pins. Place 0.1 Β΅F ceramic decoupling capacitors as close as possible to every VCCINT and VCCIO pin, with bulk 10-47 Β΅F tantalum or aluminum polymer capacitors at the board entry point. Because the device can draw up to several hundred mA during configuration, ensure the 5 V regulator has adequate headroom and transient response. For multi-FPGA designs, sequence the 5 V rail with the configuration devices to avoid partial-configuration latch-up.
The 160-pin PQFP package uses a 0.65 mm lead pitch, which is at the upper limit for fine-pitch surface-mount assembly. Use a PCB land pattern that follows IPC-7351 guidelines with a footprint pad width of approximately 0.35 mm. Apply a solder paste stencil with 0.15 mm thickness and use no-clean SAC305 lead-free paste for production. For prototyping, consider socketed adapters from manufacturers like Emulation Technology or Ironwood Electronics to avoid damaging expensive FPGAs during rework.
Estimated: configuration bitstream size for a fully utilized EPF8636AQC160-3N is approximately 95-110 Kbits, exceeding the EPC1064 (64 Kbit) capacity. Choose EPC1213 (213 Kbit) or EPC1441 (441 Kbit) for designs using 80-100% of logic resources. Configuring from parallel EPROM at system power-up requires correct nCONFIG, nSTATUS, and CONF_DONE pull-up resistors (typically 10 kΞ© to VCC) and proper JTAG chain termination per IEEE 1149.1 (BST). Mixing JTAG and passive serial configuration on the same board requires careful nCE/nCONFIG signal management.
The PQFP-160 package has a typical ΞΈJA of approximately 25-30 Β°C/W in still air, rising with reduced PCB copper area. Estimated: at 5 V VCCINT and 100% logic utilization, the device can dissipate 1.5-2.0 W, producing a junction temperature rise of 40-60 Β°C above ambient. For enclosed industrial enclosures with ambient up to 60 Β°C, attach a small clip-on heatsink or use 4-layer PCBs with continuous inner copper planes connected to the thermal pad through vias.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-minerals compliance data are not available in the verified distributor data for this obsolete part. The 'N' suffix in the MPN historically denotes lead-free terminal finish on later Altera FPGAs, but specific RoHS/REACH certificates must be requested from the manufacturer or franchised distributor at time of order. AEC-Q100 not applicable for this commercial-grade 0-70 Β°C part.
