EPF8636AQC160-4 - FLEX 8000 FPGA, 6K Gates, 160-PQFP | Intel
MPN: EPF8636AQC160-4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $381.82 | $381.82 |
| 10 | $320 | $3,200.00 |
| 100 | $268.5 | $26,850.00 |
| 500 | $225 | $112,500.00 |
| 1,000 | $198 | $198,000.00 |
Drop-in alternatives for EPF8636AQC160-4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF8636AQC160-3
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPF8636AQC160-4N
✅ Drop-In✓ In Stock
$52.3 / Unit
View Datasheet →EPF8636AQC160-3N
✅ Drop-In✓ In Stock
$29.25 / Unit
View Datasheet →EPF8452AQC160-4
✅ Drop-In✓ In Stock
$11 / Unit
View Datasheet →EPF8452AQC160-4N
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPF8452AQC160-3
✅ Drop-In✓ In Stock
$13.85 / Unit
View Datasheet →EPF8452AQC160-3AC
✅ Drop-In✓ In Stock
$14.1 / Unit
View Datasheet →EPF8636AQC160-4 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Logic Elements / Cells | 504 |
| Usable Gates | 6,000 |
| Logic Array Blocks (LABs) | 63 |
| User I/Os | 118 |
| Maximum Toggle Frequency | 125 MHz |
| Process Technology | 0.42 µm CMOS |
| Supply Voltage (Core) | 5 V |
| I/O Supply Voltage | 3.3 V or 5.0 V (MultiVolt) |
| Package | 160-pin PQFP (BQFP) |
| Operating Temperature | 0 °C to +70 °C (Commercial) |
| Configuration Method | Serial EPROM, parallel EPROM, or system controller |
| Configuration Devices | EPC1, EPC1064, EPC1213, EPC1441 |
| Speed Grade | -4 (slowest commercial) |
| Mounting Type | Surface Mount (gull-wing) |
| RoHS Status | unknown |
EPF8636AQC160-4 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | VCCIO1 — I/O supply voltage for bank 1 (3.3 V or 5.0 V) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | GND — Ground |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | DATA0 — Configuration data input (serial mode) |
| Pin 16 | nSTATUS — Configuration status (open-drain, pulled low during configuration) |
| Pin 17 | DCLK — Configuration clock input |
| Pin 18 | CONF_DONE — Configuration done indicator (open-drain) |
| Pin 19 | VCCINT — Core supply voltage (5 V) |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | VCCIO2 — I/O supply voltage for bank 2 (3.3 V or 5.0 V) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | I/O — User I/O pin (bank 2) |
| Pin 28 | I/O — User I/O pin (bank 2) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 2) |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — User I/O pin (bank 3) |
| Pin 42 | I/O — User I/O pin (bank 3) |
| Pin 43 | I/O — User I/O pin (bank 3) |
| Pin 44 | I/O — User I/O pin (bank 3) |
| Pin 45 | I/O — User I/O pin (bank 3) |
| Pin 46 | VCCIO3 — I/O supply voltage for bank 3 (3.3 V or 5.0 V) |
| Pin 47 | I/O — User I/O pin (bank 3) |
| Pin 48 | I/O — User I/O pin (bank 3) |
| Pin 49 | I/O — User I/O pin (bank 3) |
| Pin 50 | I/O — User I/O pin (bank 3) |
| Pin 51 | VCCINT — Core supply voltage (5 V) |
| Pin 52 | GND — Ground |
| Pin 53 | I/O — User I/O pin (bank 3) |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | I/O — User I/O pin (bank 3) |
| Pin 56 | I/O — User I/O pin (bank 3) |
| Pin 57 | I/O — User I/O pin (bank 3) |
| Pin 58 | I/O — User I/O pin (bank 3) |
| Pin 59 | TDI — JTAG test data input |
| Pin 60 | TMS — JTAG test mode select |
| Pin 61 | TCK — JTAG test clock |
| Pin 62 | TDO — JTAG test data output |
| Pin 63 | I/O — User I/O pin (bank 4) |
| Pin 64 | VCCIO4 — I/O supply voltage for bank 4 (3.3 V or 5.0 V) |
| Pin 65 | I/O — User I/O pin (bank 4) |
| Pin 66 | I/O — User I/O pin (bank 4) |
| Pin 67 | I/O — User I/O pin (bank 4) |
| Pin 68 | I/O — User I/O pin (bank 4) |
| Pin 69 | I/O — User I/O pin (bank 4) |
| Pin 70 | I/O — User I/O pin (bank 4) |
| Pin 71 | I/O — User I/O pin (bank 4) |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | GND — Ground |
| Pin 74 | I/O — User I/O pin (bank 4) |
| Pin 75 | I/O — User I/O pin (bank 4) |
| Pin 76 | I/O — User I/O pin (bank 4) |
| Pin 77 | I/O — User I/O pin (bank 4) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | I/O — User I/O pin (bank 4) |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | I/O — User I/O pin (bank 4) |
| Pin 82 | VCCINT — Core supply voltage (5 V) |
| Pin 83 | I/O — User I/O pin (bank 5) |
| Pin 84 | I/O — User I/O pin (bank 5) |
| Pin 85 | VCCIO5 — I/O supply voltage for bank 5 (3.3 V or 5.0 V) |
| Pin 86 | I/O — User I/O pin (bank 5) |
| Pin 87 | I/O — User I/O pin (bank 5) |
| Pin 88 | I/O — User I/O pin (bank 5) |
| Pin 89 | I/O — User I/O pin (bank 5) |
| Pin 90 | I/O — User I/O pin (bank 5) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin (bank 5) |
| Pin 93 | I/O — User I/O pin (bank 5) |
| Pin 94 | I/O — User I/O pin (bank 5) |
| Pin 95 | I/O — User I/O pin (bank 5) |
| Pin 96 | I/O — User I/O pin (bank 5) |
| Pin 97 | I/O — User I/O pin (bank 5) |
| Pin 98 | I/O — User I/O pin (bank 5) |
| Pin 99 | I/O — User I/O pin (bank 5) |
| Pin 100 | I/O — User I/O pin (bank 5) |
| Pin 101 | MSEL0 — Configuration mode select bit 0 |
| Pin 102 | MSEL1 — Configuration mode select bit 1 |
| Pin 103 | VCCINT — Core supply voltage (5 V) |
| Pin 104 | GND — Ground |
| Pin 105 | I/O — User I/O pin (bank 6) |
| Pin 106 | I/O — User I/O pin (bank 6) |
| Pin 107 | I/O — User I/O pin (bank 6) |
| Pin 108 | I/O — User I/O pin (bank 6) |
| Pin 109 | VCCIO6 — I/O supply voltage for bank 6 (3.3 V or 5.0 V) |
| Pin 110 | I/O — User I/O pin (bank 6) |
| Pin 111 | I/O — User I/O pin (bank 6) |
| Pin 112 | I/O — User I/O pin (bank 6) |
| Pin 113 | I/O — User I/O pin (bank 6) |
| Pin 114 | I/O — User I/O pin (bank 6) |
| Pin 115 | I/O — User I/O pin (bank 6) |
| Pin 116 | I/O — User I/O pin (bank 6) |
| Pin 117 | I/O — User I/O pin (bank 6) |
| Pin 118 | I/O — User I/O pin (bank 6) |
| Pin 119 | I/O — User I/O pin (bank 6) |
| Pin 120 | I/O — User I/O pin (bank 6) |
| Pin 121 | I/O — User I/O pin (bank 6) |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O pin (bank 7) |
| Pin 124 | I/O — User I/O pin (bank 7) |
| Pin 125 | VCCIO7 — I/O supply voltage for bank 7 (3.3 V or 5.0 V) |
| Pin 126 | I/O — User I/O pin (bank 7) |
| Pin 127 | I/O — User I/O pin (bank 7) |
| Pin 128 | I/O — User I/O pin (bank 7) |
| Pin 129 | I/O — User I/O pin (bank 7) |
| Pin 130 | I/O — User I/O pin (bank 7) |
| Pin 131 | I/O — User I/O pin (bank 7) |
| Pin 132 | I/O — User I/O pin (bank 7) |
| Pin 133 | VCCINT — Core supply voltage (5 V) |
| Pin 134 | GND — Ground |
| Pin 135 | I/O — User I/O pin (bank 7) |
| Pin 136 | I/O — User I/O pin (bank 7) |
| Pin 137 | I/O — User I/O pin (bank 7) |
| Pin 138 | I/O — User I/O pin (bank 7) |
| Pin 139 | I/O — User I/O pin (bank 7) |
| Pin 140 | I/O — User I/O pin (bank 7) |
| Pin 141 | I/O — User I/O pin (bank 7) |
| Pin 142 | I/O — User I/O pin (bank 7) |
| Pin 143 | I/O — User I/O pin (bank 7) |
| Pin 144 | I/O — User I/O pin (bank 7) |
| Pin 145 | I/O — User I/O pin (bank 8) |
| Pin 146 | I/O — User I/O pin (bank 8) |
| Pin 147 | VCCIO8 — I/O supply voltage for bank 8 (3.3 V or 5.0 V) |
| Pin 148 | I/O — User I/O pin (bank 8) |
| Pin 149 | I/O — User I/O pin (bank 8) |
| Pin 150 | I/O — User I/O pin (bank 8) |
| Pin 151 | I/O — User I/O pin (bank 8) |
| Pin 152 | I/O — User I/O pin (bank 8) |
| Pin 153 | I/O — User I/O pin (bank 8) |
| Pin 154 | GND — Ground |
| Pin 155 | I/O — User I/O pin (bank 8) |
| Pin 156 | I/O — User I/O pin (bank 8) |
| Pin 157 | I/O — User I/O pin (bank 8) |
| Pin 158 | I/O — User I/O pin (bank 8) |
| Pin 159 | VCCINT — Core supply voltage (5 V) |
| Pin 160 | I/O — User I/O pin (bank 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8636AQC160-4 is suitable for 6 applications: Legacy Industrial Glue Logic, Telecom Backplane Bus Bridge, Peripheral Interface Adapter, Data Acquisition Front End, 32-bit Processor Co-Processor, Legacy Equipment Retrofit.
Legacy Industrial Glue Logic
The EPF8636AQC160-4 fits legacy industrial glue-logic applications because its 6,000 usable gates, 504 logic elements, and 118 user I/Os provide ample capacity for bus-bridge, address-decode, and state-machine functions common in PLC backplanes and motor-control boards. With 125 MHz maximum toggle frequency and a 5 V core, it interfaces directly to legacy 5 V peripheral ICs without level shifters, simplifying board design. The MultiVolt I/O feature also lets one device bridge to 3.3 V processors where modern controllers have been retrofitted into older equipment.
Recommended
Telecom Backplane Bus Bridge
The EPF8636AQC160-4 is well-suited as a telecom backplane bus bridge because its 118 user I/Os support wide parallel buses, and its 5 V tolerant MultiVolt I/O pins can interface to both legacy 5 V bus transceivers and 3.3 V control logic. The 504 logic elements provide enough capacity for protocol conversion between E1/T1 framers, HDLC controllers, and processor-side DMA engines, while 125 MHz toggle frequency accommodates standard telecom line rates plus overhead. The 160-pin PQFP package keeps the part on conventional SMT assembly lines used in telecom hardware.
Recommended
Peripheral Interface Adapter
As a peripheral interface adapter, the EPF8636AQC160-4 benefits from its 118 I/O count, which supports a wide range of legacy peripherals (ISA, SCSI, parallel ports, GPIB) on a single device. The SRAM-based architecture allows in-system reconfiguration for firmware updates via JTAG, and the MultiVolt I/O feature enables direct connection to mixed-voltage peripherals without external level translation. Designers can use 504 logic elements to implement state machines, FIFOs, and interrupt controllers in a single chip, replacing multiple 74-series TTL packages.
Recommended
Data Acquisition Front End
The EPF8636AQC160-4 fits data-acquisition front ends because its 118 user I/Os accept parallel output from multi-channel ADCs, and its 504 logic elements implement digital filtering, channel multiplexing, and timing control. With 5 V I/O, it interfaces directly to legacy parallel-output ADCs without level translation, and the 125 MHz toggle frequency supports sample rates above what most 5 V ADCs can deliver. The 160-pin PQFP package provides sufficient I/O count for 16-bit-wide data buses plus dedicated control and clock pins per channel.
Recommended
32-bit Processor Co-Processor
The EPF8636AQC160-4 serves as a 32-bit processor co-processor using its 504 logic elements for custom accelerators, address-decode logic, and external bus arbitration. The 5 V core supply matches legacy 5 V processors and DSPs, while MultiVolt I/O permits direct connection to 3.3 V peripheral buses without external translation. The 118 user I/Os handle 32-bit data plus 24-32 bit address plus control signals, and SRAM-based configuration supports field upgrades via JTAG when co-processor firmware is updated alongside host processor firmware.
Recommended
Legacy Equipment Retrofit
The EPF8636AQC160-4 supports legacy equipment retrofit applications where the original board was designed against FLEX 8000 silicon and replacement parts must remain pin-compatible. Its 160-pin PQFP footprint matches the original PCB land pattern, eliminating the need for board rework during field replacements. The 5 V core and MultiVolt I/O keep compatibility with surrounding legacy analog and digital components, while SRAM-based configuration allows last-minute firmware updates when retrofitting introduces new peripheral behaviors. Distributor-only inventory makes planning essential.
Recommended
Recommended Products Summary
Engineering reference data for EPF8636AQC160-4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8636AQC160-3 | EPF8636AQC160-4N | EPF8636AQC160-3N | EPF8452AQC160-4 | EPF8452AQC160-3 |
|---|---|---|---|---|---|---|
| Package | 160-pin PQFP | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 4,500 (-25%) | 4,500 (-25%) |
| Logic Elements | 504 | 504 | 504 | 504 | 396 (-21%) | 396 (-21%) |
| Speed Grade | -4 | -3 (faster) | -4 | -3 (faster) | -4 | -3 (faster) |
| Lead-Free / RoHS Finish | Unknown / standard finish | Unknown / standard finish | Yes (N suffix = RoHS) | Yes (N suffix = RoHS) | Unknown / standard finish | Unknown / standard finish |
| User I/Os | 118 | 118 | 118 | 118 | 118 | 118 |
| Core Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
Key Differentiators
- Higher logic density than EPF8452AQC160-4 alternative (vs EPF8452AQC160-4)
- RoHS-compliant drop-in upgrade option exists (vs EPF8636AQC160-4N)
- Faster speed-grade drop-in upgrade available (vs EPF8636AQC160-3)
Design Notes
The EPF8636AQC160-4 is obsolete and not recommended for new designs. According to Intel's FLEX 8000 family discontinuance notices, last-time-buy windows have closed and only distributor-channel inventory remains. When designing new boards, select MAX II, MAX V, MAX 10, or Cyclone-series FPGAs instead; for repair or field replacement of legacy equipment, source the original part or one of the listed same-package drop-in alternatives (EPF8636AQC160-3, EPF8636AQC160-4N, EPF8636AQC160-3N).
Estimated: VCCINT (5 V core) typically draws 50-150 mA depending on logic utilization and toggle rate, while VCCIO (3.3 V or 5.0 V I/O) draws an additional 10-50 mA per bank depending on switching frequency and load. Decouple each VCCINT pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin, plus a 10 µF tantalum bulk capacitor near the device. Each VCCIO bank should have its own 0.1 µF decoupling cap to suppress switching transients on the I/O supply rail.
Do not omit the MSEL0/MSEL1 configuration-mode strap resistors - they select between serial EPROM, parallel EPROM, and microprocessor configuration modes, and floating MSEL pins cause configuration failure. Ensure nSTATUS has a 10 kΩ pull-up to VCCINT and CONF_DONE has a 10 kΩ pull-up to VCCINT per the FLEX 8000 datasheet, otherwise the device will not exit configuration cleanly. For JTAG boundary-scan testing, tie TMS high through a 10 kΩ resistor so the TAP controller enters Test-Logic-Reset at power-up.
Estimated: at maximum toggle rate with all 118 I/Os switching, total power dissipation can reach 0.5-1.0 W; the 160-pin PQFP package has a θJA of approximately 35-45 °C/W in still air, yielding a junction temperature rise of 17-45 °C above ambient. Provide a continuous ground plane on the top and bottom PCB layers under the device for thermal spreading, and place thermal vias under the die-attach pad (if present) to conduct heat to inner copper layers.
Compliance Information
The base EPF8636AQC160-4 (without N suffix) is typically a SnPb-finish part per FLEX 8000 era manufacturing; the N-suffix variants (EPF8636AQC160-4N, EPF8636AQC160-3N) provide lead-free RoHS-compliant terminal finish. AEC-Q100 is not applicable because the part is rated for commercial temperature (0 to +70 °C), not automotive.
