EPF8820AQC208-3 - FLEX 8000 FPGA, 672 LEs, 208-PQFP | Altera
Référence : EPF8820AQC208-3 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $32.75 | $327,50 |
| 100 | $24.9 | $2 490,00 |
| 250 | $21.4 | $5 350,00 |
| 500 | $18.95 | $9 475,00 |
EPF8820AQC208-3 Présentation
A Field Programmable Gate Array (FPGA) is a semiconductor IC built around an array of configurable logic blocks (CLBs/LABs) connected by programmable interconnect. FPGAs belong to the broader category of programmable logic devices (PLDs), which sit between fixed-function ASICs and discrete logic in the design hierarchy. Unlike gate arrays or standard-cell ASICs, FPGAs are reprogrammed in-circuit, accelerating prototyping and reducing non-recurring engineering (NRE) cost.
The FLEX 8000 architecture combines a fine-grained logic fabric with dedicated FastTrack interconnect and a continuous SRAM configuration memory. Each LAB contains 8 logic elements (LEs) and local interconnect, while FastTrack rows and columns provide predictable, tpd-independent delays across the device. The EPF8820AQC208-3 also features built-in JTAG (IEEE 1149.1) boundary-scan support and in-circuit reconfigurability (ICR) via external EPROM (EPC1, EPC1064, EPC1213, EPC1441) or a system controller.
Typical applications include glue-logic replacement, peripheral bus bridging, custom state-machine controllers, telecom interface glue, and industrial control front-ends. The 152 available I/Os at 5 V tolerance (commercial grade 0C to 70C) make it well suited to legacy TTL/CMOS bus interfaces. The device is also commonly deployed as a hardware accelerator for DSP pre/post-processing in cost-sensitive systems where modern FPGAs are over-spec.
When designing with this part, note that the EPF8820AQC208-3 is marked Obsolete/EOL per the latest distributor listings; only remaining stock and refurbished supply are available. Designers should validate long-term availability for new production and consider modern Cyclone or MAX series as functionally equivalent drop-in alternatives where possible.
This page synthesizes distributor pricing, pin-to-pin compatible alternatives from the Altera FLEX 8000 family, and design notes not found on the original Altera datasheet, including context on SRAM configuration and JTAG testing for legacy designs.
Alternatives de remplacement direct pour EPF8820AQC208-3 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPF8820AQC208-3 (même facteur de forme et même empreinte) — différant par Package, Process Technology, Operating Temperature, Configuration Method, Usable Gates.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPF8820AQC208-2N
✅ Remplacement direct✓ En stock
$5.1 / unité
Voir la fiche technique →EPF8820AQC208-2
✅ Remplacement direct✓ En stock
$22.8 / unité
Voir la fiche technique →EPF8820AQC160-4
✅ Remplacement direct✓ En stock
$17.95 / unité
Voir la fiche technique →EPF8820AQC160-3
✅ Remplacement direct✓ En stock
$17.95 / unité
Voir la fiche technique →EPF8820AQC160-2
✅ Remplacement direct✓ En stock
$17.9 / unité
Voir la fiche technique →EPF81188AQC208-3
✅ Remplacement direct✓ En stock
$14.2 / unité
Voir la fiche technique →EPF8820AQC208-3 Valeurs maximales et caractéristiques électriques
| Family | FLEX 8000 |
| Device Type | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | 672 |
| Usable Gates | 8,000 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 152 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Température de fonctionnement | 0 C to 70 C (Commercial) |
| Boîtier | 208-pin PQFP (Plastic Quad Flat Pack), 28 x 28 mm |
| Type de montage | Surface Mount (Gull-Wing) |
| Process Technology | CMOS SRAM |
| Configuration Method | Serial or parallel EPROM (EPC1, EPC1064, EPC1213, EPC1441), system controller |
| Boundary Scan | JTAG IEEE 1149.1 |
| In-Circuit Reconfigurability | Yes (ICR) |
| Speed Grade | -3 |
| Statut du cycle de vie | Obsolete (EOL) |
Configuration des broches de EPF8820AQC208-3
| Broche 1 | I/O — User I/O pin (bank A) |
| Broche 2 | I/O — User I/O pin (bank A) |
| Broche 3 | I/O — User I/O pin (bank A) |
| Broche 4 | I/O — User I/O pin (bank A) |
| Broche 5 | I/O — User I/O pin (bank A) |
| Broche 6 | I/O — User I/O pin (bank A) |
| Broche 7 | I/O — User I/O pin (bank A) |
| Broche 8 | I/O — User I/O pin (bank A) |
| Broche 9 | I/O — User I/O pin (bank A) |
| Broche 10 | I/O — User I/O pin (bank A) |
| Broche 11 | I/O — User I/O pin (bank A) |
| Broche 12 | I/O — User I/O pin (bank A) |
| Broche 13 | I/O — User I/O pin (bank A) |
| Broche 14 | I/O — User I/O pin (bank A) |
| Broche 15 | I/O — User I/O pin (bank A) |
| Broche 16 | VCC — 5V supply |
| Broche 17 | GND — Ground |
| Broche 18 | I/O — User I/O pin (bank B) |
| Broche 19 | I/O — User I/O pin (bank B) |
| Broche 20 | I/O — User I/O pin (bank B) |
| Broche 21 | I/O — User I/O pin (bank B) |
| Broche 22 | I/O — User I/O pin (bank B) |
| Broche 23 | I/O — User I/O pin (bank B) |
| Broche 24 | I/O — User I/O pin (bank B) |
| Broche 25 | I/O — User I/O pin (bank B) |
| Broche 26 | I/O — User I/O pin (bank B) |
| Broche 27 | I/O — User I/O pin (bank B) |
| Broche 28 | I/O — User I/O pin (bank B) |
| Broche 29 | I/O — User I/O pin (bank B) |
| Broche 30 | I/O — User I/O pin (bank B) |
| Broche 31 | I/O — User I/O pin (bank B) |
| Broche 32 | I/O — User I/O pin (bank B) |
| Broche 33 | VCC — 5V supply |
| Broche 34 | GND — Ground |
| Broche 35 | I/O — User I/O pin (bank C) |
| Broche 36 | I/O — User I/O pin (bank C) |
| Broche 37 | I/O — User I/O pin (bank C) |
| Broche 38 | I/O — User I/O pin (bank C) |
| Broche 39 | I/O — User I/O pin (bank C) |
| Broche 40 | I/O — User I/O pin (bank C) |
| Broche 41 | I/O — User I/O pin (bank C) |
| Broche 42 | I/O — User I/O pin (bank C) |
| Broche 43 | I/O — User I/O pin (bank C) |
| Broche 44 | I/O — User I/O pin (bank C) |
| Broche 45 | I/O — User I/O pin (bank C) |
| Broche 46 | I/O — User I/O pin (bank C) |
| Broche 47 | I/O — User I/O pin (bank C) |
| Broche 48 | I/O — User I/O pin (bank C) |
| Broche 49 | I/O — User I/O pin (bank C) |
| Broche 50 | VCC — 5V supply |
| Broche 51 | GND — Ground |
| Broche 52 | I/O — User I/O pin (bank D) |
| Broche 53 | I/O — User I/O pin (bank D) |
| Broche 54 | I/O — User I/O pin (bank D) |
| Broche 55 | I/O — User I/O pin (bank D) |
| Broche 56 | I/O — User I/O pin (bank D) |
| Broche 57 | I/O — User I/O pin (bank D) |
| Broche 58 | I/O — User I/O pin (bank D) |
| Broche 59 | I/O — User I/O pin (bank D) |
| Broche 60 | I/O — User I/O pin (bank D) |
| Broche 61 | I/O — User I/O pin (bank D) |
| Broche 62 | I/O — User I/O pin (bank D) |
| Broche 63 | I/O — User I/O pin (bank D) |
| Broche 64 | I/O — User I/O pin (bank D) |
| Broche 65 | I/O — User I/O pin (bank D) |
| Broche 66 | I/O — User I/O pin (bank D) |
| Broche 67 | VCC — 5V supply |
| Broche 68 | GND — Ground |
| Broche 69 | I/O — User I/O pin (bank E) |
| Broche 70 | I/O — User I/O pin (bank E) |
| Broche 71 | I/O — User I/O pin (bank E) |
| Broche 72 | I/O — User I/O pin (bank E) |
| Broche 73 | I/O — User I/O pin (bank E) |
| Broche 74 | I/O — User I/O pin (bank E) |
| Broche 75 | I/O — User I/O pin (bank E) |
| Broche 76 | I/O — User I/O pin (bank E) |
| Broche 77 | I/O — User I/O pin (bank E) |
| Broche 78 | I/O — User I/O pin (bank E) |
| Broche 79 | I/O — User I/O pin (bank E) |
| Broche 80 | I/O — User I/O pin (bank E) |
| Broche 81 | I/O — User I/O pin (bank E) |
| Broche 82 | I/O — User I/O pin (bank E) |
| Broche 83 | I/O — User I/O pin (bank E) |
| Broche 84 | VCC — 5V supply |
| Broche 85 | GND — Ground |
| Broche 86 | I/O — User I/O pin (bank F) |
| Broche 87 | I/O — User I/O pin (bank F) |
| Broche 88 | I/O — User I/O pin (bank F) |
| Broche 89 | I/O — User I/O pin (bank F) |
| Broche 90 | I/O — User I/O pin (bank F) |
| Broche 91 | I/O — User I/O pin (bank F) |
| Broche 92 | I/O — User I/O pin (bank F) |
| Broche 93 | I/O — User I/O pin (bank F) |
| Broche 94 | I/O — User I/O pin (bank F) |
| Broche 95 | I/O — User I/O pin (bank F) |
| Broche 96 | I/O — User I/O pin (bank F) |
| Broche 97 | I/O — User I/O pin (bank F) |
| Broche 98 | I/O — User I/O pin (bank F) |
| Broche 99 | I/O — User I/O pin (bank F) |
| Broche 100 | I/O — User I/O pin (bank F) |
| Broche 101 | VCC — 5V supply |
| Broche 102 | GND — Ground |
| Broche 103 | I/O — User I/O pin (bank G) |
| Broche 104 | I/O — User I/O pin (bank G) |
| Broche 105 | I/O — User I/O pin (bank G) |
| Broche 106 | I/O — User I/O pin (bank G) |
| Broche 107 | I/O — User I/O pin (bank G) |
| Broche 108 | I/O — User I/O pin (bank G) |
| Broche 109 | I/O — User I/O pin (bank G) |
| Broche 110 | I/O — User I/O pin (bank G) |
| Broche 111 | I/O — User I/O pin (bank G) |
| Broche 112 | I/O — User I/O pin (bank G) |
| Broche 113 | I/O — User I/O pin (bank G) |
| Broche 114 | I/O — User I/O pin (bank G) |
| Broche 115 | I/O — User I/O pin (bank G) |
| Broche 116 | I/O — User I/O pin (bank G) |
| Broche 117 | I/O — User I/O pin (bank G) |
| Broche 118 | VCC — 5V supply |
| Broche 119 | GND — Ground |
| Broche 120 | I/O — User I/O pin (bank H) |
| Broche 121 | I/O — User I/O pin (bank H) |
| Broche 122 | I/O — User I/O pin (bank H) |
| Broche 123 | I/O — User I/O pin (bank H) |
| Broche 124 | I/O — User I/O pin (bank H) |
| Broche 125 | I/O — User I/O pin (bank H) |
| Broche 126 | I/O — User I/O pin (bank H) |
| Broche 127 | I/O — User I/O pin (bank H) |
| Broche 128 | I/O — User I/O pin (bank H) |
| Broche 129 | I/O — User I/O pin (bank H) |
| Broche 130 | I/O — User I/O pin (bank H) |
| Broche 131 | I/O — User I/O pin (bank H) |
| Broche 132 | I/O — User I/O pin (bank H) |
| Broche 133 | I/O — User I/O pin (bank H) |
| Broche 134 | I/O — User I/O pin (bank H) |
| Broche 135 | VCC — 5V supply |
| Broche 136 | GND — Ground |
| Broche 137 | I/O — User I/O pin (bank A) |
| Broche 138 | I/O — User I/O pin (bank A) |
| Broche 139 | I/O — User I/O pin (bank A) |
| Broche 140 | I/O — User I/O pin (bank A) |
| Broche 141 | I/O — User I/O pin (bank A) |
| Broche 142 | I/O — User I/O pin (bank A) |
| Broche 143 | I/O — User I/O pin (bank A) |
| Broche 144 | I/O — User I/O pin (bank A) |
| Broche 145 | I/O — User I/O pin (bank A) |
| Broche 146 | I/O — User I/O pin (bank A) |
| Broche 147 | I/O — User I/O pin (bank A) |
| Broche 148 | I/O — User I/O pin (bank A) |
| Broche 149 | I/O — User I/O pin (bank A) |
| Broche 150 | I/O — User I/O pin (bank A) |
| Broche 151 | I/O — User I/O pin (bank A) |
| Broche 152 | VCC — 5V supply |
| Broche 153 | GND — Ground |
| Broche 154 | I/O — User I/O pin (bank B) |
| Broche 155 | I/O — User I/O pin (bank B) |
| Broche 156 | I/O — User I/O pin (bank B) |
| Broche 157 | I/O — User I/O pin (bank B) |
| Broche 158 | I/O — User I/O pin (bank B) |
| Broche 159 | I/O — User I/O pin (bank B) |
| Broche 160 | I/O — User I/O pin (bank B) |
| Broche 161 | I/O — User I/O pin (bank B) |
| Broche 162 | I/O — User I/O pin (bank B) |
| Broche 163 | I/O — User I/O pin (bank B) |
| Broche 164 | I/O — User I/O pin (bank B) |
| Broche 165 | I/O — User I/O pin (bank B) |
| Broche 166 | I/O — User I/O pin (bank B) |
| Broche 167 | I/O — User I/O pin (bank B) |
| Broche 168 | I/O — User I/O pin (bank B) |
| Broche 169 | VCC — 5V supply |
| Broche 170 | GND — Ground |
| Broche 171 | I/O — User I/O pin (bank C) |
| Broche 172 | I/O — User I/O pin (bank C) |
| Broche 173 | I/O — User I/O pin (bank C) |
| Broche 174 | I/O — User I/O pin (bank C) |
| Broche 175 | I/O — User I/O pin (bank C) |
| Broche 176 | I/O — User I/O pin (bank C) |
| Broche 177 | I/O — User I/O pin (bank C) |
| Broche 178 | I/O — User I/O pin (bank C) |
| Broche 179 | I/O — User I/O pin (bank C) |
| Broche 180 | I/O — User I/O pin (bank C) |
| Broche 181 | I/O — User I/O pin (bank C) |
| Broche 182 | I/O — User I/O pin (bank C) |
| Broche 183 | I/O — User I/O pin (bank C) |
| Broche 184 | I/O — User I/O pin (bank C) |
| Broche 185 | I/O — User I/O pin (bank C) |
| Broche 186 | VCC — 5V supply |
| Broche 187 | GND — Ground |
| Broche 188 | I/O — User I/O pin (bank D) |
| Broche 189 | I/O — User I/O pin (bank D) |
| Broche 190 | I/O — User I/O pin (bank D) |
| Broche 191 | I/O — User I/O pin (bank D) |
| Broche 192 | I/O — User I/O pin (bank D) |
| Broche 193 | I/O — User I/O pin (bank D) |
| Broche 194 | I/O — User I/O pin (bank D) |
| Broche 195 | I/O — User I/O pin (bank D) |
| Broche 196 | I/O — User I/O pin (bank D) |
| Broche 197 | I/O — User I/O pin (bank D) |
| Broche 198 | I/O — User I/O pin (bank D) |
| Broche 199 | I/O — User I/O pin (bank D) |
| Broche 200 | I/O — User I/O pin (bank D) |
| Broche 201 | I/O — User I/O pin (bank D) |
| Broche 202 | I/O — User I/O pin (bank D) |
| Broche 203 | VCC — 5V supply |
| Broche 204 | GND — Ground |
| Broche 205 | nCONFIG — Configuration control (active low) |
| Broche 206 | nSTATUS — Configuration status (active low) |
| Broche 207 | CONF_DONE — Configuration done indicator |
| Broche 208 | TCK — JTAG test clock (IEEE 1149.1) |
Applications typiques
EPF8820AQC208-3 convient pour 6 applications: Legacy Telecom Glue Logic, Industrial Control Front-End, Custom Peripheral Bus Bridge, Hardware State-Machine Controller, DSP Pre/Post-Processing Accelerator, Test & Measurement Fixture Logic.
Legacy Telecom Glue Logic
The EPF8820AQC208-3 fits telecom glue-logic designs thanks to its 152 5V-tolerant I/Os that connect directly to legacy TTL/CMOS bus peripherals without level shifters. With 672 LEs across 84 LABs it bridges E1/T1 framers, HDLC controllers, and time-slot interchangers at line rates up to tens of MHz. Unlike smaller CPLDs, the FastTrack interconnect delivers uniform tpd across the die, simplifying timing closure when fanning out to multiple bus segments. A typical circuit places the EPF8820AQC208-3 between a framer IC and a backplane transceiver, with JTAG access for boundary-scan production test.
Recommandé
Industrial Control Front-End
The EPF8820AQC208-3 is widely deployed in industrial PLC and motion-control front-ends because its 5 V I/O tolerance mates directly with 24 V isolated digital inputs and 5 V sensor buses via external buffers. The 672-LE capacity is sufficient for PWM generation, encoder decoding (incremental and SSI), and custom deterministic state machines. The commercial 0C to 70C operating range suits cabinet-mounted controllers, while JTAG boundary-scan accelerates in-circuit test on densely populated backplanes. Designers benefit from FastTrack predictable routing when fanning out 100+ control signals across multiple connector banks.
Recommandé
Custom Peripheral Bus Bridge
With 152 user I/Os and 8,000 usable gates, the EPF8820AQC208-3 can implement multi-master bus bridges between legacy ISA, PC/104, and proprietary peripheral buses. Its SRAM-based fabric lets designers iterate bridge protocols during system bring-up without mask charges, and JTAG enables live reconfiguration of bus protocol state machines during field debug. The 208-pin PQFP footprint offers ample 5V-tolerant I/O for both address/data multiplexing and interrupt/control signal replication. Compared to a discrete 74-series implementation, the EPF8820AQC208-3 reduces PCB area by 5-10x and consolidates timing-critical glue into one timing-closed device.
Recommandé
Hardware State-Machine Controller
The EPF8820AQC208-3 excels at implementing complex, multi-state control sequencers that would otherwise require dozens of PAL/GAL devices. With 84 LABs it can hold 50+ parallel finite state machines plus their interlock logic, and its SRAM configuration enables late-stage firmware changes. The 5V I/Os interface directly to opto-isolated industrial outputs, while the JTAG TAP controller provides a window into internal states during integration testing. Designers typically use MAX+PLUS II to enter state machines as AHDL/Verilog and synthesize into the device. Compared to a microcontroller, the FPGA delivers deterministic single-clock-cycle state transitions without RTOS overhead.
Recommandé
DSP Pre/Post-Processing Accelerator
In cost-sensitive DSP subsystems, the EPF8820AQC208-3 acts as a hardware accelerator for FIR filtering, data formatting, and protocol encapsulation offloaded from a host DSP. Its 672 LEs support 16-tap FIR filters or parallel CRC engines running at full 5V I/O speeds, and FastTrack interconnect ensures uniform sample-to-sample timing. Designers often pair the FPGA with a serial EEPROM configuration device (EPC1 or EPC1064) for fast power-up boot, and route JTAG to a header for emulator access. Compared to a DSP software implementation, the FPGA variant typically delivers 3-10x throughput per MHz while freeing the host DSP for control tasks.
Recommandé
Test & Measurement Fixture Logic
The EPF8820AQC208-3 is a strong fit for ATE pin-card and bed-of-nails fixture logic, where 152 5V I/Os connect to UUT pins through relays and the FPGA orchestrates stimulus/response sequences. Its SRAM fabric lets test engineers swap personality bitstreams for different UUTs in seconds, and JTAG provides full visibility into FPGA states during fixture bring-up. The commercial temperature range suits bench fixtures, while the 208-PQFP is easy to socket or rework. Designers appreciate the deterministic FastTrack delays when sequencing parallel test vectors to multiple UUT pins at once.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPF8820AQC208-3 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPF8820AQC208-2N | EPF8820AQC208-2 | EPF8820AQC160-4 | EPF8820AQC160-3 | EPF8820AQC160-2 | EPF81188AQC208-3 |
|---|---|---|---|---|---|---|---|
| Package | 208-pin PQFP (28x28 mm) | 208-pin PQFP - same | 208-pin PQFP - same | 160-pin PQFP - same family | 160-pin PQFP - same family | 160-pin PQFP - same family | 208-pin PQFP - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Logic Elements | 672 | 672 | 672 | 672 | 672 | 672 | 1,188 |
| Speed Grade | -3 | -2 (faster) | -2 (faster) | -4 (fastest) | -3 (same) | -2 (faster) | -3 (same) |
| Usable Gates | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 12,000 |
| User I/Os | 152 | 152 | 152 | 120 | 120 | 120 | 171 |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
Principaux différenciateurs
- Higher logic density with same 208-PQFP footprint (vs EPF81188AQC208-3)
- Faster speed grade variant available (vs EPF8820AQC208-2N)
- Reduced pin-count footprint option (vs EPF8820AQC160-3)
Notes de conception
The EPF8820AQC208-3 requires a clean 5 V supply (4.75 V to 5.25 V) with adequate decoupling. Place one 0.1 uF ceramic capacitor per VCC pin pair and one bulk 22-47 uF tantalum or aluminum polymer capacitor near each VCC bank. SRAM-based FPGAs draw surge currents during configuration; the bulk capacitor prevents VCC droop that can cause configuration failures. Estimated: at 25 MHz toggle activity on 100 I/Os, ICCINT is typically 150-250 mA; size the regulator for at least 1.5x this value plus headroom for inrush.
Use a 4-layer PCB with dedicated VCC and GND planes for the EPF8820AQC208-3. Route all 152 user I/Os on short, matched traces and avoid 90-degree bends to reduce reflections on 5V TTL-level signals. Place configuration EPROM (EPC1/EPC1064/EPC1213/EPC1441) within 50 mm of the FPGA to keep configuration traces short. Expose JTAG pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE) to a 0.1-inch header or 10-pin JTAG ribbon for debug and production programming.
Because the EPF8820AQC208-3 is marked Obsolete/EOL, do not use it for new production designs without a written last-time-buy commitment from Altera/Intel. Modern designs should target Cyclone IV, MAX II, or MAX V as functionally equivalent replacements, but note that none of these are pin-compatible - a PCB redesign is required. For legacy support, qualify a single broker-sourced lot and verify authenticity before use.
The 208-pin PQFP package has relatively long lead inductance (~5-7 nH) that can create ground bounce on heavily-loaded outputs. Use series damping resistors (22-33 ohm) on outputs driving backplane connectors, and avoid simultaneous switching of more than 16 outputs per bank. For clock distribution, dedicate one global FastTrack buffer per clock domain to minimize skew.
Informations de conformité
The EPF8820AQC208-3 is an obsolete Altera FLEX 8000 device; compliance documentation is not explicitly listed in current distributor data. The PQFP-208 package is typically Pb-free for legacy Altera commercial parts, but RoHS/REACH status is not confirmed by current datasheets.
