EPF8820AQC208-2 - FLEX 8000 FPGA, 8K Gates, 152 I/O, 5V, PQFP-208 | Altera
MPN: EPF8820AQC208-2 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38.5 | $385.00 |
| 100 | $31.2 | $3,120.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $22.8 | $22,800.00 |
Drop-in alternatives for EPF8820AQC208-2 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPF8820AQC208-2 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (Intel PSG) |
| Family | FLEX 8000 |
| Device Type | FPGA - Field Programmable Gate Array |
| Usable Gates | 8,000 |
| Logic Cells / Registers | 672 |
| Logic Array Blocks (LABs) | 84 (8 LEs per LAB) |
| User I/Os | 152 |
| Maximum Operating Frequency | 125 MHz |
| Supply Voltage | 5 V |
| Logic Family | CMOS |
| Operating Temperature | 0 C to 70 C (Commercial) |
| Package Type | 208-BFQFP / 208-Pin PQFP (FQFP) |
| Package Code | FQFP, gull-wing terminals |
| Mounting Type | Surface Mount |
| Process Technology | CMOS, SRAM-based configuration |
| Configuration Method | In-Circuit Reconfigurability (ICR) via external device; SRAM-volatile |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| Grade | Commercial |
EPF8820AQC208-2 Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | VCC β 5V supply |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | I/O β User I/O (bank 2) |
| Pin 14 | I/O β User I/O (bank 2) |
| Pin 15 | I/O β User I/O (bank 2) |
| Pin 16 | I/O β User I/O (bank 2) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O (bank 2) |
| Pin 19 | I/O β User I/O (bank 2) |
| Pin 20 | I/O β User I/O (bank 2) |
| Pin 21 | I/O β User I/O (bank 2) |
| Pin 22 | VCC β 5V supply |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | I/O β User I/O (bank 2) |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O (bank 3) |
| Pin 29 | I/O β User I/O (bank 3) |
| Pin 30 | I/O β User I/O (bank 3) |
| Pin 31 | I/O β User I/O (bank 3) |
| Pin 32 | I/O β User I/O (bank 3) |
| Pin 33 | VCC β 5V supply |
| Pin 34 | I/O β User I/O (bank 3) |
| Pin 35 | I/O β User I/O (bank 3) |
| Pin 36 | I/O β User I/O (bank 3) |
| Pin 37 | I/O β User I/O (bank 3) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O (bank 3) |
| Pin 40 | I/O β User I/O (bank 3) |
| Pin 41 | I/O β User I/O (bank 4) |
| Pin 42 | I/O β User I/O (bank 4) |
| Pin 43 | I/O β User I/O (bank 4) |
| Pin 44 | VCC β 5V supply |
| Pin 45 | I/O β User I/O (bank 4) |
| Pin 46 | I/O β User I/O (bank 4) |
| Pin 47 | I/O β User I/O (bank 4) |
| Pin 48 | I/O β User I/O (bank 4) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O (bank 4) |
| Pin 51 | I/O β User I/O (bank 4) |
| Pin 52 | I/O β User I/O (bank 4) |
| Pin 53 | I/O β User I/O (bank 4) |
| Pin 54 | I/O β User I/O (bank 5) |
| Pin 55 | VCC β 5V supply |
| Pin 56 | I/O β User I/O (bank 5) |
| Pin 57 | I/O β User I/O (bank 5) |
| Pin 58 | I/O β User I/O (bank 5) |
| Pin 59 | I/O β User I/O (bank 5) |
| Pin 60 | I/O β User I/O (bank 5) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O (bank 5) |
| Pin 63 | I/O β User I/O (bank 5) |
| Pin 64 | I/O β User I/O (bank 5) |
| Pin 65 | I/O β User I/O (bank 5) |
| Pin 66 | VCC β 5V supply |
| Pin 67 | I/O β User I/O (bank 5) |
| Pin 68 | I/O β User I/O (bank 6) |
| Pin 69 | I/O β User I/O (bank 6) |
| Pin 70 | I/O β User I/O (bank 6) |
| Pin 71 | I/O β User I/O (bank 6) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O (bank 6) |
| Pin 74 | I/O β User I/O (bank 6) |
| Pin 75 | I/O β User I/O (bank 6) |
| Pin 76 | I/O β User I/O (bank 6) |
| Pin 77 | I/O β User I/O (bank 6) |
| Pin 78 | VCC β 5V supply |
| Pin 79 | I/O β User I/O (bank 6) |
| Pin 80 | I/O β User I/O (bank 6) |
| Pin 81 | I/O β User I/O (bank 7) |
| Pin 82 | I/O β User I/O (bank 7) |
| Pin 83 | I/O β User I/O (bank 7) |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β User I/O (bank 7) |
| Pin 86 | I/O β User I/O (bank 7) |
| Pin 87 | I/O β User I/O (bank 7) |
| Pin 88 | I/O β User I/O (bank 7) |
| Pin 89 | I/O β User I/O (bank 7) |
| Pin 90 | VCC β 5V supply |
| Pin 91 | I/O β User I/O (bank 7) |
| Pin 92 | I/O β User I/O (bank 7) |
| Pin 93 | I/O β User I/O (bank 7) |
| Pin 94 | I/O β User I/O (bank 7) |
| Pin 95 | GND β Ground |
| Pin 96 | I/O β User I/O (bank 7) |
| Pin 97 | I/O β User I/O (bank 8) |
| Pin 98 | I/O β User I/O (bank 8) |
| Pin 99 | I/O β User I/O (bank 8) |
| Pin 100 | I/O β User I/O (bank 8) |
| Pin 101 | VCC β 5V supply |
| Pin 102 | I/O β User I/O (bank 8) |
| Pin 103 | I/O β User I/O (bank 8) |
| Pin 104 | I/O β User I/O (bank 8) |
| Pin 105 | I/O β User I/O (bank 8) |
| Pin 106 | GND β Ground |
| Pin 107 | I/O β User I/O (bank 8) |
| Pin 108 | I/O β User I/O (bank 8) |
| Pin 109 | I/O β User I/O (bank 8) |
| Pin 110 | I/O β User I/O (bank 8) |
| Pin 111 | I/O β User I/O (bank 8) |
| Pin 112 | VCC β 5V supply |
| Pin 113 | I/O β User I/O (bank 8) |
| Pin 114 | I/O β User I/O (bank 8) |
| Pin 115 | DCLK β Configuration clock input (dedicated) |
| Pin 116 | nCONFIG β Configuration control input (dedicated) |
| Pin 117 | nSTATUS β Configuration status output (dedicated) |
| Pin 118 | CONF_DONE β Configuration done output (dedicated) |
| Pin 119 | TDI β JTAG test data input |
| Pin 120 | TMS β JTAG test mode select |
| Pin 121 | TCK β JTAG test clock |
| Pin 122 | TDO β JTAG test data output |
| Pin 123 | GND β Ground |
| Pin 124 | I/O β User I/O (bank 1) |
| Pin 125 | I/O β User I/O (bank 1) |
| Pin 126 | I/O β User I/O (bank 1) |
| Pin 127 | I/O β User I/O (bank 1) |
| Pin 128 | VCC β 5V supply |
| Pin 129 | I/O β User I/O (bank 1) |
| Pin 130 | I/O β User I/O (bank 1) |
| Pin 131 | I/O β User I/O (bank 1) |
| Pin 132 | I/O β User I/O (bank 1) |
| Pin 133 | GND β Ground |
| Pin 134 | I/O β User I/O (bank 1) |
| Pin 135 | I/O β User I/O (bank 1) |
| Pin 136 | I/O β User I/O (bank 1) |
| Pin 137 | I/O β User I/O (bank 1) |
| Pin 138 | I/O β User I/O (bank 2) |
| Pin 139 | VCC β 5V supply |
| Pin 140 | I/O β User I/O (bank 2) |
| Pin 141 | I/O β User I/O (bank 2) |
| Pin 142 | I/O β User I/O (bank 2) |
| Pin 143 | I/O β User I/O (bank 2) |
| Pin 144 | I/O β User I/O (bank 2) |
| Pin 145 | GND β Ground |
| Pin 146 | I/O β User I/O (bank 2) |
| Pin 147 | I/O β User I/O (bank 2) |
| Pin 148 | I/O β User I/O (bank 2) |
| Pin 149 | I/O β User I/O (bank 2) |
| Pin 150 | I/O β User I/O (bank 2) |
| Pin 151 | VCC β 5V supply |
| Pin 152 | I/O β User I/O (bank 3) |
| Pin 153 | I/O β User I/O (bank 3) |
| Pin 154 | I/O β User I/O (bank 3) |
| Pin 155 | I/O β User I/O (bank 3) |
| Pin 156 | GND β Ground |
| Pin 157 | I/O β User I/O (bank 3) |
| Pin 158 | I/O β User I/O (bank 3) |
| Pin 159 | I/O β User I/O (bank 3) |
| Pin 160 | I/O β User I/O (bank 3) |
| Pin 161 | I/O β User I/O (bank 3) |
| Pin 162 | VCC β 5V supply |
| Pin 163 | I/O β User I/O (bank 3) |
| Pin 164 | I/O β User I/O (bank 4) |
| Pin 165 | I/O β User I/O (bank 4) |
| Pin 166 | I/O β User I/O (bank 4) |
| Pin 167 | I/O β User I/O (bank 4) |
| Pin 168 | GND β Ground |
| Pin 169 | I/O β User I/O (bank 4) |
| Pin 170 | I/O β User I/O (bank 4) |
| Pin 171 | I/O β User I/O (bank 4) |
| Pin 172 | I/O β User I/O (bank 4) |
| Pin 173 | I/O β User I/O (bank 4) |
| Pin 174 | VCC β 5V supply |
| Pin 175 | I/O β User I/O (bank 4) |
| Pin 176 | I/O β User I/O (bank 5) |
| Pin 177 | I/O β User I/O (bank 5) |
| Pin 178 | I/O β User I/O (bank 5) |
| Pin 179 | I/O β User I/O (bank 5) |
| Pin 180 | I/O β User I/O (bank 5) |
| Pin 181 | GND β Ground |
| Pin 182 | I/O β User I/O (bank 5) |
| Pin 183 | I/O β User I/O (bank 5) |
| Pin 184 | I/O β User I/O (bank 5) |
| Pin 185 | I/O β User I/O (bank 5) |
| Pin 186 | VCC β 5V supply |
| Pin 187 | I/O β User I/O (bank 5) |
| Pin 188 | I/O β User I/O (bank 6) |
| Pin 189 | I/O β User I/O (bank 6) |
| Pin 190 | I/O β User I/O (bank 6) |
| Pin 191 | I/O β User I/O (bank 6) |
| Pin 192 | GND β Ground |
| Pin 193 | I/O β User I/O (bank 6) |
| Pin 194 | I/O β User I/O (bank 6) |
| Pin 195 | I/O β User I/O (bank 6) |
| Pin 196 | I/O β User I/O (bank 6) |
| Pin 197 | I/O β User I/O (bank 6) |
| Pin 198 | VCC β 5V supply |
| Pin 199 | I/O β User I/O (bank 6) |
| Pin 200 | I/O β User I/O (bank 7) |
| Pin 201 | I/O β User I/O (bank 7) |
| Pin 202 | I/O β User I/O (bank 7) |
| Pin 203 | I/O β User I/O (bank 7) |
| Pin 204 | GND β Ground |
| Pin 205 | I/O β User I/O (bank 7) |
| Pin 206 | I/O β User I/O (bank 7) |
| Pin 207 | I/O β User I/O (bank 7) |
| Pin 208 | I/O β User I/O (bank 7) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820AQC208-2 is suitable for 6 applications: Legacy 5V Bus-Interface Bridging, Glue Logic Replacement for 74-Series TTL/CMOS, Industrial Control State Machines, ASIC Prototyping and Pre-Silicon Verification, Legacy Telecom and Datacom Equipment, Test & Measurement Instrumentation.
Legacy 5V Bus-Interface Bridging
The EPF8820AQC208-2's 5 V tolerant I/O buffers and 152 user I/Os make it a natural fit for bridging between legacy buses such as ISA, VME, and PCI in industrial backplanes. Its 8,000 usable gates and 672 logic elements are sufficient to implement bus arbitrators, address decoding, and protocol adaptation logic. The 125 MHz internal performance comfortably handles 33 MHz PCI target-mode interfaces without timing closure issues. Unlike modern 3.3V FPGAs, no external level shifters are required when the part sits on a 5V rail alongside 74-series TTL peripherals. Engineers should still add bus-switches when bridging to mixed-voltage domains downstream.
Recommended
Glue Logic Replacement for 74-Series TTL/CMOS
The EPF8820AQC208-2 can absorb dozens of discrete 74LS/74HC/MSI packages - decoders, multiplexers, latches, and small state machines - into a single 5V FPGA, simplifying PCB layout and reducing BOM cost. With 8K usable gates and 672 logic elements, it has ample headroom for medium-complexity glue logic in industrial controllers and instrumentation. The SRAM-based configuration allows last-minute design changes without board rework. Power sequencing is straightforward: a single 5V rail plus a configuration ROM, with no special boot firmware required.
Recommended
Industrial Control State Machines
The EPF8820AQC208-2's 672 logic elements and rich register set make it well suited to medium-complexity state machines used in PLCs, motor controllers, and process automation. Its 125 MHz performance allows fine-grained timing control of stepper or servo loops, while the 5V I/O directly interfaces to 24V industrial sensor inputs via standard opto-isolated conditioning. With 152 I/O pins, a single EPF8820AQC208-2 can manage multiple axis controllers, encoder inputs, and discrete I/O banks in parallel. Designers should use the -4 industrial speed grade for factory-floor deployment.
Recommended
ASIC Prototyping and Pre-Silicon Verification
With 8,000 usable gates and SRAM-based in-circuit reconfigurability (ICR), the EPF8820AQC208-2 is used as an ASIC prototype vehicle where designers can iterate RTL designs in hours rather than weeks. Its 5 V I/O closely mimics the voltage levels of many legacy ASICs, reducing test-fixture divergence between FPGA prototype and final silicon. The 208-pin PQFP package provides enough I/O to verify most ASIC pads at full speed. JTAG boundary scan (IEEE 1149.1) enables fast board-level interconnect testing during ASIC bring-up.
Recommended
Legacy Telecom and Datacom Equipment
Telecom and datacom equipment built in the late 1990s frequently used FLEX 8000 FPGAs as protocol controllers, framer engines, and TDM bus arbiters. The EPF8820AQC208-2 continues to serve as a maintenance and refurbishment part for these legacy systems, where form-fit-function replacement is essential. Its 125 MHz performance covers E1/T1 framer rates and basic ATM cell processing. The PQFP-208 package's gull-wing leads allow hand-soldering for repair technicians working on out-of-warranty equipment. Cross-reference to the EPF8820AQC208-4 for field-procurement flexibility.
Recommended
Test & Measurement Instrumentation
The EPF8820AQC208-2 finds use in older test equipment - logic analyzers, protocol analyzers, and ATE fixture controllers - where 5V logic levels interface directly to the device under test. Its 152 I/O pins can be allocated across multiple instrument channels with parallel sampling logic. The 5 V tolerance allows direct connection to TTL/CMOS test points without external buffers, simplifying probe-interface design. Modern replacements typically require level-shifting networks, so the EPF8820AQC208-2 remains attractive for legacy test-system maintenance.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820AQC208-2 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820AQC208-4 | EPF8820AQC160-2 | EPF8820ABC225-4 | EPF8820AGC192-2 | EPF8636AQC208-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 208-Pin PQFP | 208-Pin PQFP (same) | 160-Pin PQFP (different) | BGA-225 (different) | 192-Pin PQFP (different) | 208-Pin PQFP (same) |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Usable Gates | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 6,000 |
| Logic Elements (LEs) | 672 | 672 | 672 | 672 | 672 | 432 |
| User I/Os | 152 | 152 | 120 | 171 (BGA) | 148 | 152 |
| Maximum Frequency | 125 MHz | ~110 MHz (-4 speed grade) | 125 MHz | ~110 MHz | 125 MHz | 125 MHz |
| Operating Temperature | 0 C to 70 C (Commercial) | -40 C to +85 C (Industrial) | 0 C to 70 C (Commercial) | -40 C to +85 C (Industrial) | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Maximized I/O density in the 208-pin PQFP FLEX 8000 family (vs EPF8820AQC160-2)
- Same-die drop-in alternative with industrial temperature grade (vs EPF8820AQC208-4)
- Maximum gate density within 208-pin PQFP FLEX 8000 footprint (vs EPF8636AQC208-2)
Design Notes
The EPF8820AQC208-2 is SRAM-volatile - the configuration is lost on every power-down and must be reloaded from a serial configuration ROM (EPC1441PC8 or similar) or via JTAG on power-up. Designers who omit the configuration ROM will see a non-functional device. Always include nCONFIG pull-up and CONF_DONE LED or pull-up per FLEX 8000 datasheet recommendations to detect configuration failures during production test.
Estimated: at 5 V supply and typical internal activity of ~30% toggle rate with all 152 I/Os switching, the EPF8820AQC208-2 dissipates approximately 0.8-1.2 W. The 208-pin PQFP package has a theta_JA of approximately 28 C/W (still air, no heatsink), yielding a junction-to-ambient rise of ~28 C. Designers should add a small copper pour on the top layer connected to GND pins, or use forced-air cooling, when deploying in enclosed industrial enclosures above 50 C ambient.
Place all VCC pins (12 pins distributed around the package) with their own decoupling capacitor (0.1 uF ceramic in parallel with 10 uF bulk). Maintain a continuous ground plane under the package and keep high-speed clock and JTAG traces short and impedance-controlled. PQFP-208 gull-wing leads have a 0.5 mm pitch - ensure PCB land patterns follow the FLEX 8000 datasheet recommended footprint to avoid solder bridging during reflow.
Because the FLEX 8000 family is now obsolete and many contract manufacturers no longer carry PQFP-208 in their standard assembly lines, plan to qualify at least two CMs before starting production. Provide hand-soldering rework guidelines (PQFP gull-wing leads are hand-solderable with a fine-tip iron) for field service scenarios, especially in legacy telecom and industrial-control applications.
Compliance Information
RoHS, REACH, lead-free and halogen-free status not specified in the verified distributor data. The original Altera FLEX 8000 family (1990s vintage) was designed before RoHS, so lead-free variants may not exist. AEC-Q100 is not applicable (FPGA, not an automotive-qualified part). Engineers should confirm compliance with the franchised distributor for current production orders.
