EPF8820AQC208-3 - FLEX 8000 FPGA, 672 LEs, 208-PQFP | Altera
部品番号: EPF8820AQC208-3 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $24.9 | $2,490.00 |
| 250 | $21.4 | $5,350.00 |
| 500 | $18.95 | $9,475.00 |
EPF8820AQC208-3 概要
A Field Programmable Gate Array (FPGA) is a semiconductor IC built around an array of configurable logic blocks (CLBs/LABs) connected by programmable interconnect. FPGAs belong to the broader category of programmable logic devices (PLDs), which sit between fixed-function ASICs and discrete logic in the design hierarchy. Unlike gate arrays or standard-cell ASICs, FPGAs are reprogrammed in-circuit, accelerating prototyping and reducing non-recurring engineering (NRE) cost.
The FLEX 8000 architecture combines a fine-grained logic fabric with dedicated FastTrack interconnect and a continuous SRAM configuration memory. Each LAB contains 8 logic elements (LEs) and local interconnect, while FastTrack rows and columns provide predictable, tpd-independent delays across the device. The EPF8820AQC208-3 also features built-in JTAG (IEEE 1149.1) boundary-scan support and in-circuit reconfigurability (ICR) via external EPROM (EPC1, EPC1064, EPC1213, EPC1441) or a system controller.
Typical applications include glue-logic replacement, peripheral bus bridging, custom state-machine controllers, telecom interface glue, and industrial control front-ends. The 152 available I/Os at 5 V tolerance (commercial grade 0C to 70C) make it well suited to legacy TTL/CMOS bus interfaces. The device is also commonly deployed as a hardware accelerator for DSP pre/post-processing in cost-sensitive systems where modern FPGAs are over-spec.
When designing with this part, note that the EPF8820AQC208-3 is marked Obsolete/EOL per the latest distributor listings; only remaining stock and refurbished supply are available. Designers should validate long-term availability for new production and consider modern Cyclone or MAX series as functionally equivalent drop-in alternatives where possible.
This page synthesizes distributor pricing, pin-to-pin compatible alternatives from the Altera FLEX 8000 family, and design notes not found on the original Altera datasheet, including context on SRAM configuration and JTAG testing for legacy designs.
ドロップイン代替品: EPF8820AQC208-3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPF8820AQC208-3 （同一形状・フットプリント） — 相違点: Package, Process Technology, Operating Temperature, Configuration Method, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPF8820AQC208-2N
✅ ドロップイン✓ 在庫あり
$5.1 / 個
データシートを見る →EPF8820AQC208-2
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →EPF8820AQC160-4
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPF8820AQC160-3
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPF8820AQC160-2
✅ ドロップイン✓ 在庫あり
$17.9 / 個
データシートを見る →EPF81188AQC208-3
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →EPF8820AQC208-3 最大定格＆電気的特性
| Family | FLEX 8000 |
| Device Type | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | 672 |
| Usable Gates | 8,000 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 152 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| 動作温度 | 0 C to 70 C (Commercial) |
| パッケージ | 208-pin PQFP (Plastic Quad Flat Pack), 28 x 28 mm |
| 実装タイプ | Surface Mount (Gull-Wing) |
| Process Technology | CMOS SRAM |
| Configuration Method | Serial or parallel EPROM (EPC1, EPC1064, EPC1213, EPC1441), system controller |
| Boundary Scan | JTAG IEEE 1149.1 |
| In-Circuit Reconfigurability | Yes (ICR) |
| Speed Grade | -3 |
| ライフサイクル状態 | Obsolete (EOL) |
EPF8820AQC208-3 ピン構成
| ピン 1 | I/O — User I/O pin (bank A) |
| ピン 2 | I/O — User I/O pin (bank A) |
| ピン 3 | I/O — User I/O pin (bank A) |
| ピン 4 | I/O — User I/O pin (bank A) |
| ピン 5 | I/O — User I/O pin (bank A) |
| ピン 6 | I/O — User I/O pin (bank A) |
| ピン 7 | I/O — User I/O pin (bank A) |
| ピン 8 | I/O — User I/O pin (bank A) |
| ピン 9 | I/O — User I/O pin (bank A) |
| ピン 10 | I/O — User I/O pin (bank A) |
| ピン 11 | I/O — User I/O pin (bank A) |
| ピン 12 | I/O — User I/O pin (bank A) |
| ピン 13 | I/O — User I/O pin (bank A) |
| ピン 14 | I/O — User I/O pin (bank A) |
| ピン 15 | I/O — User I/O pin (bank A) |
| ピン 16 | VCC — 5V supply |
| ピン 17 | GND — Ground |
| ピン 18 | I/O — User I/O pin (bank B) |
| ピン 19 | I/O — User I/O pin (bank B) |
| ピン 20 | I/O — User I/O pin (bank B) |
| ピン 21 | I/O — User I/O pin (bank B) |
| ピン 22 | I/O — User I/O pin (bank B) |
| ピン 23 | I/O — User I/O pin (bank B) |
| ピン 24 | I/O — User I/O pin (bank B) |
| ピン 25 | I/O — User I/O pin (bank B) |
| ピン 26 | I/O — User I/O pin (bank B) |
| ピン 27 | I/O — User I/O pin (bank B) |
| ピン 28 | I/O — User I/O pin (bank B) |
| ピン 29 | I/O — User I/O pin (bank B) |
| ピン 30 | I/O — User I/O pin (bank B) |
| ピン 31 | I/O — User I/O pin (bank B) |
| ピン 32 | I/O — User I/O pin (bank B) |
| ピン 33 | VCC — 5V supply |
| ピン 34 | GND — Ground |
| ピン 35 | I/O — User I/O pin (bank C) |
| ピン 36 | I/O — User I/O pin (bank C) |
| ピン 37 | I/O — User I/O pin (bank C) |
| ピン 38 | I/O — User I/O pin (bank C) |
| ピン 39 | I/O — User I/O pin (bank C) |
| ピン 40 | I/O — User I/O pin (bank C) |
| ピン 41 | I/O — User I/O pin (bank C) |
| ピン 42 | I/O — User I/O pin (bank C) |
| ピン 43 | I/O — User I/O pin (bank C) |
| ピン 44 | I/O — User I/O pin (bank C) |
| ピン 45 | I/O — User I/O pin (bank C) |
| ピン 46 | I/O — User I/O pin (bank C) |
| ピン 47 | I/O — User I/O pin (bank C) |
| ピン 48 | I/O — User I/O pin (bank C) |
| ピン 49 | I/O — User I/O pin (bank C) |
| ピン 50 | VCC — 5V supply |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O pin (bank D) |
| ピン 53 | I/O — User I/O pin (bank D) |
| ピン 54 | I/O — User I/O pin (bank D) |
| ピン 55 | I/O — User I/O pin (bank D) |
| ピン 56 | I/O — User I/O pin (bank D) |
| ピン 57 | I/O — User I/O pin (bank D) |
| ピン 58 | I/O — User I/O pin (bank D) |
| ピン 59 | I/O — User I/O pin (bank D) |
| ピン 60 | I/O — User I/O pin (bank D) |
| ピン 61 | I/O — User I/O pin (bank D) |
| ピン 62 | I/O — User I/O pin (bank D) |
| ピン 63 | I/O — User I/O pin (bank D) |
| ピン 64 | I/O — User I/O pin (bank D) |
| ピン 65 | I/O — User I/O pin (bank D) |
| ピン 66 | I/O — User I/O pin (bank D) |
| ピン 67 | VCC — 5V supply |
| ピン 68 | GND — Ground |
| ピン 69 | I/O — User I/O pin (bank E) |
| ピン 70 | I/O — User I/O pin (bank E) |
| ピン 71 | I/O — User I/O pin (bank E) |
| ピン 72 | I/O — User I/O pin (bank E) |
| ピン 73 | I/O — User I/O pin (bank E) |
| ピン 74 | I/O — User I/O pin (bank E) |
| ピン 75 | I/O — User I/O pin (bank E) |
| ピン 76 | I/O — User I/O pin (bank E) |
| ピン 77 | I/O — User I/O pin (bank E) |
| ピン 78 | I/O — User I/O pin (bank E) |
| ピン 79 | I/O — User I/O pin (bank E) |
| ピン 80 | I/O — User I/O pin (bank E) |
| ピン 81 | I/O — User I/O pin (bank E) |
| ピン 82 | I/O — User I/O pin (bank E) |
| ピン 83 | I/O — User I/O pin (bank E) |
| ピン 84 | VCC — 5V supply |
| ピン 85 | GND — Ground |
| ピン 86 | I/O — User I/O pin (bank F) |
| ピン 87 | I/O — User I/O pin (bank F) |
| ピン 88 | I/O — User I/O pin (bank F) |
| ピン 89 | I/O — User I/O pin (bank F) |
| ピン 90 | I/O — User I/O pin (bank F) |
| ピン 91 | I/O — User I/O pin (bank F) |
| ピン 92 | I/O — User I/O pin (bank F) |
| ピン 93 | I/O — User I/O pin (bank F) |
| ピン 94 | I/O — User I/O pin (bank F) |
| ピン 95 | I/O — User I/O pin (bank F) |
| ピン 96 | I/O — User I/O pin (bank F) |
| ピン 97 | I/O — User I/O pin (bank F) |
| ピン 98 | I/O — User I/O pin (bank F) |
| ピン 99 | I/O — User I/O pin (bank F) |
| ピン 100 | I/O — User I/O pin (bank F) |
| ピン 101 | VCC — 5V supply |
| ピン 102 | GND — Ground |
| ピン 103 | I/O — User I/O pin (bank G) |
| ピン 104 | I/O — User I/O pin (bank G) |
| ピン 105 | I/O — User I/O pin (bank G) |
| ピン 106 | I/O — User I/O pin (bank G) |
| ピン 107 | I/O — User I/O pin (bank G) |
| ピン 108 | I/O — User I/O pin (bank G) |
| ピン 109 | I/O — User I/O pin (bank G) |
| ピン 110 | I/O — User I/O pin (bank G) |
| ピン 111 | I/O — User I/O pin (bank G) |
| ピン 112 | I/O — User I/O pin (bank G) |
| ピン 113 | I/O — User I/O pin (bank G) |
| ピン 114 | I/O — User I/O pin (bank G) |
| ピン 115 | I/O — User I/O pin (bank G) |
| ピン 116 | I/O — User I/O pin (bank G) |
| ピン 117 | I/O — User I/O pin (bank G) |
| ピン 118 | VCC — 5V supply |
| ピン 119 | GND — Ground |
| ピン 120 | I/O — User I/O pin (bank H) |
| ピン 121 | I/O — User I/O pin (bank H) |
| ピン 122 | I/O — User I/O pin (bank H) |
| ピン 123 | I/O — User I/O pin (bank H) |
| ピン 124 | I/O — User I/O pin (bank H) |
| ピン 125 | I/O — User I/O pin (bank H) |
| ピン 126 | I/O — User I/O pin (bank H) |
| ピン 127 | I/O — User I/O pin (bank H) |
| ピン 128 | I/O — User I/O pin (bank H) |
| ピン 129 | I/O — User I/O pin (bank H) |
| ピン 130 | I/O — User I/O pin (bank H) |
| ピン 131 | I/O — User I/O pin (bank H) |
| ピン 132 | I/O — User I/O pin (bank H) |
| ピン 133 | I/O — User I/O pin (bank H) |
| ピン 134 | I/O — User I/O pin (bank H) |
| ピン 135 | VCC — 5V supply |
| ピン 136 | GND — Ground |
| ピン 137 | I/O — User I/O pin (bank A) |
| ピン 138 | I/O — User I/O pin (bank A) |
| ピン 139 | I/O — User I/O pin (bank A) |
| ピン 140 | I/O — User I/O pin (bank A) |
| ピン 141 | I/O — User I/O pin (bank A) |
| ピン 142 | I/O — User I/O pin (bank A) |
| ピン 143 | I/O — User I/O pin (bank A) |
| ピン 144 | I/O — User I/O pin (bank A) |
| ピン 145 | I/O — User I/O pin (bank A) |
| ピン 146 | I/O — User I/O pin (bank A) |
| ピン 147 | I/O — User I/O pin (bank A) |
| ピン 148 | I/O — User I/O pin (bank A) |
| ピン 149 | I/O — User I/O pin (bank A) |
| ピン 150 | I/O — User I/O pin (bank A) |
| ピン 151 | I/O — User I/O pin (bank A) |
| ピン 152 | VCC — 5V supply |
| ピン 153 | GND — Ground |
| ピン 154 | I/O — User I/O pin (bank B) |
| ピン 155 | I/O — User I/O pin (bank B) |
| ピン 156 | I/O — User I/O pin (bank B) |
| ピン 157 | I/O — User I/O pin (bank B) |
| ピン 158 | I/O — User I/O pin (bank B) |
| ピン 159 | I/O — User I/O pin (bank B) |
| ピン 160 | I/O — User I/O pin (bank B) |
| ピン 161 | I/O — User I/O pin (bank B) |
| ピン 162 | I/O — User I/O pin (bank B) |
| ピン 163 | I/O — User I/O pin (bank B) |
| ピン 164 | I/O — User I/O pin (bank B) |
| ピン 165 | I/O — User I/O pin (bank B) |
| ピン 166 | I/O — User I/O pin (bank B) |
| ピン 167 | I/O — User I/O pin (bank B) |
| ピン 168 | I/O — User I/O pin (bank B) |
| ピン 169 | VCC — 5V supply |
| ピン 170 | GND — Ground |
| ピン 171 | I/O — User I/O pin (bank C) |
| ピン 172 | I/O — User I/O pin (bank C) |
| ピン 173 | I/O — User I/O pin (bank C) |
| ピン 174 | I/O — User I/O pin (bank C) |
| ピン 175 | I/O — User I/O pin (bank C) |
| ピン 176 | I/O — User I/O pin (bank C) |
| ピン 177 | I/O — User I/O pin (bank C) |
| ピン 178 | I/O — User I/O pin (bank C) |
| ピン 179 | I/O — User I/O pin (bank C) |
| ピン 180 | I/O — User I/O pin (bank C) |
| ピン 181 | I/O — User I/O pin (bank C) |
| ピン 182 | I/O — User I/O pin (bank C) |
| ピン 183 | I/O — User I/O pin (bank C) |
| ピン 184 | I/O — User I/O pin (bank C) |
| ピン 185 | I/O — User I/O pin (bank C) |
| ピン 186 | VCC — 5V supply |
| ピン 187 | GND — Ground |
| ピン 188 | I/O — User I/O pin (bank D) |
| ピン 189 | I/O — User I/O pin (bank D) |
| ピン 190 | I/O — User I/O pin (bank D) |
| ピン 191 | I/O — User I/O pin (bank D) |
| ピン 192 | I/O — User I/O pin (bank D) |
| ピン 193 | I/O — User I/O pin (bank D) |
| ピン 194 | I/O — User I/O pin (bank D) |
| ピン 195 | I/O — User I/O pin (bank D) |
| ピン 196 | I/O — User I/O pin (bank D) |
| ピン 197 | I/O — User I/O pin (bank D) |
| ピン 198 | I/O — User I/O pin (bank D) |
| ピン 199 | I/O — User I/O pin (bank D) |
| ピン 200 | I/O — User I/O pin (bank D) |
| ピン 201 | I/O — User I/O pin (bank D) |
| ピン 202 | I/O — User I/O pin (bank D) |
| ピン 203 | VCC — 5V supply |
| ピン 204 | GND — Ground |
| ピン 205 | nCONFIG — Configuration control (active low) |
| ピン 206 | nSTATUS — Configuration status (active low) |
| ピン 207 | CONF_DONE — Configuration done indicator |
| ピン 208 | TCK — JTAG test clock (IEEE 1149.1) |
主な用途
EPF8820AQC208-3 の用途: 6 件s: Legacy Telecom Glue Logic, Industrial Control Front-End, Custom Peripheral Bus Bridge, Hardware State-Machine Controller, DSP Pre/Post-Processing Accelerator, Test & Measurement Fixture Logic.
Legacy Telecom Glue Logic
The EPF8820AQC208-3 fits telecom glue-logic designs thanks to its 152 5V-tolerant I/Os that connect directly to legacy TTL/CMOS bus peripherals without level shifters. With 672 LEs across 84 LABs it bridges E1/T1 framers, HDLC controllers, and time-slot interchangers at line rates up to tens of MHz. Unlike smaller CPLDs, the FastTrack interconnect delivers uniform tpd across the die, simplifying timing closure when fanning out to multiple bus segments. A typical circuit places the EPF8820AQC208-3 between a framer IC and a backplane transceiver, with JTAG access for boundary-scan production test.
おすすめ
Industrial Control Front-End
The EPF8820AQC208-3 is widely deployed in industrial PLC and motion-control front-ends because its 5 V I/O tolerance mates directly with 24 V isolated digital inputs and 5 V sensor buses via external buffers. The 672-LE capacity is sufficient for PWM generation, encoder decoding (incremental and SSI), and custom deterministic state machines. The commercial 0C to 70C operating range suits cabinet-mounted controllers, while JTAG boundary-scan accelerates in-circuit test on densely populated backplanes. Designers benefit from FastTrack predictable routing when fanning out 100+ control signals across multiple connector banks.
おすすめ
Custom Peripheral Bus Bridge
With 152 user I/Os and 8,000 usable gates, the EPF8820AQC208-3 can implement multi-master bus bridges between legacy ISA, PC/104, and proprietary peripheral buses. Its SRAM-based fabric lets designers iterate bridge protocols during system bring-up without mask charges, and JTAG enables live reconfiguration of bus protocol state machines during field debug. The 208-pin PQFP footprint offers ample 5V-tolerant I/O for both address/data multiplexing and interrupt/control signal replication. Compared to a discrete 74-series implementation, the EPF8820AQC208-3 reduces PCB area by 5-10x and consolidates timing-critical glue into one timing-closed device.
おすすめ
Hardware State-Machine Controller
The EPF8820AQC208-3 excels at implementing complex, multi-state control sequencers that would otherwise require dozens of PAL/GAL devices. With 84 LABs it can hold 50+ parallel finite state machines plus their interlock logic, and its SRAM configuration enables late-stage firmware changes. The 5V I/Os interface directly to opto-isolated industrial outputs, while the JTAG TAP controller provides a window into internal states during integration testing. Designers typically use MAX+PLUS II to enter state machines as AHDL/Verilog and synthesize into the device. Compared to a microcontroller, the FPGA delivers deterministic single-clock-cycle state transitions without RTOS overhead.
おすすめ
DSP Pre/Post-Processing Accelerator
In cost-sensitive DSP subsystems, the EPF8820AQC208-3 acts as a hardware accelerator for FIR filtering, data formatting, and protocol encapsulation offloaded from a host DSP. Its 672 LEs support 16-tap FIR filters or parallel CRC engines running at full 5V I/O speeds, and FastTrack interconnect ensures uniform sample-to-sample timing. Designers often pair the FPGA with a serial EEPROM configuration device (EPC1 or EPC1064) for fast power-up boot, and route JTAG to a header for emulator access. Compared to a DSP software implementation, the FPGA variant typically delivers 3-10x throughput per MHz while freeing the host DSP for control tasks.
おすすめ
Test & Measurement Fixture Logic
The EPF8820AQC208-3 is a strong fit for ATE pin-card and bed-of-nails fixture logic, where 152 5V I/Os connect to UUT pins through relays and the FPGA orchestrates stimulus/response sequences. Its SRAM fabric lets test engineers swap personality bitstreams for different UUTs in seconds, and JTAG provides full visibility into FPGA states during fixture bring-up. The commercial temperature range suits bench fixtures, while the 208-PQFP is easy to socket or rework. Designers appreciate the deterministic FastTrack delays when sequencing parallel test vectors to multiple UUT pins at once.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPF8820AQC208-3 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPF8820AQC208-2N | EPF8820AQC208-2 | EPF8820AQC160-4 | EPF8820AQC160-3 | EPF8820AQC160-2 | EPF81188AQC208-3 |
|---|---|---|---|---|---|---|---|
| Package | 208-pin PQFP (28x28 mm) | 208-pin PQFP - same | 208-pin PQFP - same | 160-pin PQFP - same family | 160-pin PQFP - same family | 160-pin PQFP - same family | 208-pin PQFP - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 | FLEX 8000 |
| Logic Elements | 672 | 672 | 672 | 672 | 672 | 672 | 1,188 |
| Speed Grade | -3 | -2 (faster) | -2 (faster) | -4 (fastest) | -3 (same) | -2 (faster) | -3 (same) |
| Usable Gates | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 12,000 |
| User I/Os | 152 | 152 | 152 | 120 | 120 | 120 | 171 |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
主な差別化要因
- Higher logic density with same 208-PQFP footprint （vs EPF81188AQC208-3)
- Faster speed grade variant available （vs EPF8820AQC208-2N)
- Reduced pin-count footprint option （vs EPF8820AQC160-3)
設計ノート
The EPF8820AQC208-3 requires a clean 5 V supply (4.75 V to 5.25 V) with adequate decoupling. Place one 0.1 uF ceramic capacitor per VCC pin pair and one bulk 22-47 uF tantalum or aluminum polymer capacitor near each VCC bank. SRAM-based FPGAs draw surge currents during configuration; the bulk capacitor prevents VCC droop that can cause configuration failures. Estimated: at 25 MHz toggle activity on 100 I/Os, ICCINT is typically 150-250 mA; size the regulator for at least 1.5x this value plus headroom for inrush.
Use a 4-layer PCB with dedicated VCC and GND planes for the EPF8820AQC208-3. Route all 152 user I/Os on short, matched traces and avoid 90-degree bends to reduce reflections on 5V TTL-level signals. Place configuration EPROM (EPC1/EPC1064/EPC1213/EPC1441) within 50 mm of the FPGA to keep configuration traces short. Expose JTAG pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE) to a 0.1-inch header or 10-pin JTAG ribbon for debug and production programming.
Because the EPF8820AQC208-3 is marked Obsolete/EOL, do not use it for new production designs without a written last-time-buy commitment from Altera/Intel. Modern designs should target Cyclone IV, MAX II, or MAX V as functionally equivalent replacements, but note that none of these are pin-compatible - a PCB redesign is required. For legacy support, qualify a single broker-sourced lot and verify authenticity before use.
The 208-pin PQFP package has relatively long lead inductance (~5-7 nH) that can create ground bounce on heavily-loaded outputs. Use series damping resistors (22-33 ohm) on outputs driving backplane connectors, and avoid simultaneous switching of more than 16 outputs per bank. For clock distribution, dedicate one global FastTrack buffer per clock domain to minimize skew.
コンプライアンス情報
The EPF8820AQC208-3 is an obsolete Altera FLEX 8000 device; compliance documentation is not explicitly listed in current distributor data. The PQFP-208 package is typically Pb-free for legacy Altera commercial parts, but RoHS/REACH status is not confirmed by current datasheets.
