EPF8820AQC160-3 - 8K Gates FLEX 8000 FPGA, 120 I/O, 5V | Intel
MPN: EPF8820AQC160-3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $21.1 | $10,550.00 |
| 1,000 | $17.95 | $17,950.00 |
Drop-in alternatives for EPF8820AQC160-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPF8820AQC160-2
β Drop-Inβ In Stock
$17.9 / Unit
View Datasheet βEPF8636AQC160-3
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPF8452AQC160-3
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPF8820AQC160-3 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Usable Gates | 8,000 |
| Logic Elements / Cells | 672 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 120 (per Mouser/DigiKey) |
| User I/Os (alt source) | 152 (per digchip BGA-225 variant listing) |
| Registers | 282 to 1,500 |
| Process Technology | 0.42 um CMOS |
| Supply Voltage | 5 V |
| Speed Grade | -3 |
| Maximum Frequency | 125 MHz |
| Package | 160-BQFP (PQFP) |
| Operating Temperature | 0C to +70C (Commercial) |
| Configuration | In-Circuit Reconfigurable (ICR) via EPC devices or JTAG |
| Bus Compliance | PCI SIG PCI Local Bus |
| Mounting Type | Surface Mount |
EPF8820AQC160-3 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank-dependent) |
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| Pin 21 | VCC β 5 V supply |
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| Pin 41 | GND β Ground |
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| Pin 61 | VCC β 5 V supply |
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| Pin 81 | GND β Ground |
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| Pin 101 | VCC β 5 V supply |
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| Pin 121 | GND β Ground |
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| Pin 141 | VCC β 5 V supply |
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| Pin 160 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820AQC160-3 is suitable for 6 applications: PCI Local Bus Bridge / Peripheral Controller, Embedded Glue Logic / System Integration, ASIC Prototyping and Design Validation, Industrial Control and Automation Backplanes, Legacy Telecom and Datacom Adapter Cards, High-Density State-Machine Replacement.
PCI Local Bus Bridge / Peripheral Controller
The EPF8820AQC160-3's 8,000 usable gates, 672 logic cells, and full PCI SIG PCI Local Bus compliance make it well-suited for 32-bit/33 MHz PCI peripheral and bridge designs. The 120 user I/Os comfortably accommodate a 32-bit address/data bus plus control signals, parity, and interrupt lines. Place the FPGA between a host CPU and a downstream peripheral bus; the integrated PCI-compliant I/O drivers meet the AC timing required by PCI add-in cards. The -3 speed grade reliably handles 33 MHz PCI with margin; for 66 MHz PCI move to the -2 speed grade (EPF8820AQC160-2). The 5 V supply aligns with classic PCI slot power, eliminating level-shifters.
Recommended
Embedded Glue Logic / System Integration
Replace dozens of 74-series TTL and CMOS glue-logic chips with a single EPF8820AQC160-3 to reduce board area, BOM count, and design complexity. With 672 logic cells and 1,500 registers, the device can absorb address decoding, bus arbitration, state machines, FIFO controllers, and interrupt controllers that would otherwise occupy a quarter-square-inch of board. The 5 V tolerant I/O is TTL-compatible, allowing direct connection to legacy peripherals without level translation. Designers can iterate the logic in days rather than weeks by re-spinning only the configuration bitstream, not the PCB. The 160-BQFP package is hand-solderable for prototypes.
Recommended
ASIC Prototyping and Design Validation
Use the EPF8820AQC160-3 as a fast-turnaround prototype for an ASIC under development, validating register-transfer-level (RTL) logic in real silicon before committing to mask costs. The 125 MHz fmax and 282-1,500 flip-flops support medium-complexity datapath and control logic typical of industrial controller ASICs. Designers benefit from the in-circuit reconfigurability: a design bug discovered in system test can be patched by reloading a new bitstream via JTAG in minutes. Once the ASIC silicon returns, the FPGA can be repurposed for the next prototype or kept as a low-volume production fallback.
Recommended
Industrial Control and Automation Backplanes
The 0C to +70C commercial operating range and 5 V supply tolerance suit the EPF8820AQC160-3 for industrial backplane controllers, VMEbus adapters, and PLC I/O expansion cards. With 120 I/Os the device can drive multi-drop RS-485 transceivers, parallel ADC/DAC interfaces, and opto-isolated digital I/O modules. The PCI compliance simplifies integration with industrial PCs and SBCs. Predictable FastTrack Interconnect timing allows designers to close timing at 25-33 MHz without manual place-and-route, shortening industrial design cycles.
Recommended
Legacy Telecom and Datacom Adapter Cards
The EPF8820AQC160-3 was widely deployed in 1990s telecom and datacom adapter cards, including ISA/PCI bridge cards, SCSI controllers, and multi-port serial cards. Its 5 V operation matches the bus voltage of legacy PCs and workstations, and the PCI compliance simplifies driver development. For maintenance and repair of installed equipment, sourcing the EPF8820AQC160-3 via obsolete-parts distributors keeps legacy systems operational. The 160-BQFP is a familiar footprint for rework technicians familiar with vintage hardware.
Recommended
High-Density State-Machine Replacement
Replace complex state machines previously implemented as dozens of PALs, GALs, or discrete MSI logic with a single EPF8820AQC160-3. The 672 logic cells and 1,500 registers can model large Mealy or Moore state machines with hundreds of states, including Huffman-coded state encoding for minimum transition counts. Designers describe the state machine in VHDL or Verilog and synthesize to the FLEX 8000 architecture using Altera MAX+PLUS II or Quartus tools. The 125 MHz fmax supports high-speed control loops in motor drives, instrument front-ends, and protocol converters.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820AQC160-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820AQC160-2 | EPF8636AQC160-3 | EPF8452AQC160-3 |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 160-BQFP | 160-BQFP (same) | 160-BQFP (same) | 160-BQFP (same) |
| Usable Gates | 8,000 | 8,000 | 6,000 | 4,000 |
| Logic Cells | 672 | 672 | 504 | 336 |
| Speed Grade | -3 | -2 (faster) | -3 | -3 |
| User I/Os | 120 | 120 | 120 | 120 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Maximum Frequency | 125 MHz | 125 MHz (faster -2 grade) | 125 MHz | 125 MHz |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- True drop-in replacement available in same 160-BQFP footprint (vs EPF8820AQC160-2)
- Higher gate density than sibling FLEX 8000 family members (vs EPF8452AQC160-3)
- Full PCI SIG compliance at 33 MHz (vs EPF8636AQC160-3)
Design Notes
The EPF8820AQC160-3 requires a stable 5 V supply (4.75 V to 5.25 V). Place 0.1 uF decoupling capacitors as close as possible to every VCC pin (4 pins total: 21, 61, 101, 141) and bulk-decouple the PCB with 10-100 uF tantalum capacitors. The FLEX 8000 family has high inrush current during configuration; ensure the 5 V regulator can supply at least 500 mA peak. Add a power-on reset supervisor (e.g., MAX706) to hold the FPGA in reset until VCC stabilizes. According to the FLEX 8000 datasheet, VCC must ramp monotonically; partial-voltage power-up can latch the device into an undefined state.
Route configuration signals (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) away from high-speed switching nets and keep them as short as possible. The JTAG signals (TCK, TMS, TDI, TDO) require 10 kohm pull-ups on TMS, TDI, and nCONFIG per IEEE 1149.1. Place the configuration EPROM (e.g., EPC1064) within 100 mm of the FPGA to avoid signal-integrity issues. The 160-BQFP package requires a 4-layer PCB with ground plane for EMI suppression; ground return paths under clock and address/data nets must be continuous.
Do not confuse the -3 speed grade with -4 or -2: each grade changes internal timing parameters and fmax by 12-15%. The EPF8820AQC160-3 (160-BQFP) is not pin-compatible with the EPF8820ABC225-4 (225-BGA) or EPF8820AGC192-2 (192-PQFP); migrating to those variants requires full PCB rework. Do not assume 3.3 V I/O compatibility: this is a 5 V part and will be damaged by 3.3 V signals applied without level translation. The 'C' in AQC160 indicates commercial temperature (0-70C); industrial designs require the 'I' suffix variant which is not available in 160-BQFP.
Compliance Information
Legacy Altera FLEX 8000 family part predates RoHS requirements; most variants contain lead-based solder. Not AEC-Q100 qualified (commercial-grade only). Compliance values reflect legacy part status; verify with specific lot documentation if compliance certification is required.
