EPM570GM256I5N - 570 LE MAX II CPLD, 256-MBGA | Intel (Altera)
Référence : EPM570GM256I5N ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $39.76 | $39,76 |
| 10 | $35.5 | $355,00 |
| 100 | $28.95 | $2 895,00 |
| 500 | $24.8 | $12 400,00 |
| 1 000 | $21.4 | $21 400,00 |
EPM570GM256I5N Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash-based programmable logic device that occupies the architectural middle ground between small SPLDs and large FPGAs. It belongs to the broader Programmable Logic Device (PLD) family, providing instant-on behavior (no boot time), deterministic timing, and high drive strength on every pin. Within the system hierarchy, CPLDs sit alongside ASICs, FPGAs, and microcontrollers in the digital logic IC category, typically used as glue logic, bus bridges, I/O expanders, and power-up sequencers.
Key features include MultiVolt core support (1.71 V to 1.89 V internal supply with mixed-voltage I/O banks), an embedded User Flash Memory (UFM) block of 8 Kbits for non-volatile data storage, and enhanced in-system programmability. The device also offers JTAG boundary-scan (IEEE 1149.1), 4-input look-up tables, and robust 3.3 V PCI-compatible I/O. Compared with traditional EEPROM-based CPLDs, the flash-based MAX II architecture reduces standby current to approximately 50 µA per macrocell and provides instant-on configuration in under 1 ms.
Typical applications include I/O expansion for microcontrollers, bus interface bridging (e.g., parallel-to-parallel voltage translation), power-up and power-sequencing controllers, board-level glue logic replacement, and configuration management for downstream FPGAs. The 256-MBGA package enables dense board layouts while exposing 160 user I/Os - sufficient to replace several discrete logic ICs.
When designing with this device, ensure the JTAG chain accommodates the device ID and that decoupling follows the MAX II handbook recommendation of 0.1 µF and 10 µF capacitors near each supply pin. Programming files should be generated with Quartus II or the latest Intel Quartus Prime Lite Edition, and unused pins should be configured as outputs driving ground for noise immunity. The instant-on non-volatile flash makes it ideal for safety-critical applications where deterministic power-up behavior is mandatory.
Alternatives de remplacement direct pour EPM570GM256I5N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM570GM256I5N (même facteur de forme et même empreinte) — différant par Process Technology, Operating Temperature, Package, RoHS Status, Maximum Operating Frequency.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM570GM256C5N
✅ Remplacement direct✓ En stock
$18.6 / unité
Voir la fiche technique →EPM570GF256I5N
✅ Remplacement direct✓ En stock
$24.1 / unité
Voir la fiche technique →EPM570F256I5N
✅ Remplacement direct✓ En stock
$19.85 / unité
Voir la fiche technique →EPM570GM100I5N
✅ Remplacement direct✓ En stock
$8.55 / unité
Voir la fiche technique →EPM570F100I5N
✅ Remplacement direct✓ En stock
$13.4 / unité
Voir la fiche technique →EPM570GM256I5N Valeurs maximales et caractéristiques électriques
| Device Family | MAX II |
| Series | MAX II G |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| User I/Os | 160 |
| Propagation Delay (tpd) | 5.4 ns (max) |
| Internal Supply Voltage | 1.71 V to 1.89 V |
| User Flash Memory (UFM) | 8 Kbits |
| Programmable Type | In-System Programmable (ISP) |
| Température de fonctionnement | -40 C to +100 C (TJ, industrial) |
| Package Type | 256-TFBGA (MBGA), 11x11 mm |
| Type de montage | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free, RoHS compliant) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| Process Technology | 6-layer-metal flash CMOS |
Configuration des broches de EPM570GM256I5N
| Broche A1 | I/O — User I/O bank 1 |
| Broche A2 | I/O — User I/O bank 1 |
| Broche A3 | I/O — User I/O bank 1 |
| Broche A4 | VCCIO1 — I/O bank 1 supply |
| Broche A5 | I/O — User I/O bank 1 |
| Broche A6 | GND — Ground |
| Broche A7 | I/O — User I/O bank 2 |
| Broche A8 | I/O — User I/O bank 2 |
| Broche A9 | VCCIO2 — I/O bank 2 supply |
| Broche A10 | I/O — User I/O bank 2 |
| Broche A11 | I/O — User I/O bank 2 |
| Broche B1 | I/O — User I/O bank 1 |
| Broche B2 | I/O — User I/O bank 1 |
| Broche B3 | I/O — User I/O bank 1 |
| Broche B4 | VCCINT — Core supply 1.71-1.89 V |
| Broche B5 | I/O — User I/O bank 1 |
| Broche B6 | TDI — JTAG test data in |
| Broche B7 | TMS — JTAG test mode select |
| Broche B8 | TCK — JTAG test clock |
| Broche B9 | I/O — User I/O bank 2 |
| Broche B10 | I/O — User I/O bank 2 |
| Broche B11 | I/O — User I/O bank 2 |
| Broche C1 | I/O — User I/O bank 1 |
| Broche C2 | I/O — User I/O bank 1 |
| Broche C3 | I/O — User I/O bank 1 |
| Broche C4 | I/O — User I/O bank 1 |
| Broche C5 | GND — Ground |
| Broche C6 | TDO — JTAG test data out |
| Broche C7 | I/O — User I/O bank 2 |
| Broche C8 | I/O — User I/O bank 2 |
| Broche C9 | I/O — User I/O bank 2 |
| Broche C10 | I/O — User I/O bank 2 |
| Broche C11 | I/O — User I/O bank 2 |
| Broche D1 | I/O — User I/O bank 1 |
| Broche D2 | I/O — User I/O bank 1 |
| Broche D3 | I/O — User I/O bank 1 |
| Broche D4 | I/O — User I/O bank 1 |
| Broche D5 | I/O — User I/O bank 1 |
| Broche D6 | GND — Ground |
| Broche D7 | I/O — User I/O bank 2 |
| Broche D8 | I/O — User I/O bank 2 |
| Broche D9 | I/O — User I/O bank 2 |
| Broche D10 | I/O — User I/O bank 2 |
| Broche D11 | I/O — User I/O bank 2 |
| Broche E1 | I/O — User I/O bank 3 |
| Broche E2 | I/O — User I/O bank 3 |
| Broche E3 | I/O — User I/O bank 3 |
| Broche E4 | I/O — User I/O bank 3 |
| Broche E5 | I/O — User I/O bank 3 |
| Broche E6 | VCCIO3 — I/O bank 3 supply |
| Broche E7 | I/O — User I/O bank 4 |
| Broche E8 | I/O — User I/O bank 4 |
| Broche E9 | I/O — User I/O bank 4 |
| Broche E10 | I/O — User I/O bank 4 |
| Broche E11 | I/O — User I/O bank 4 |
| Broche F1 | I/O — User I/O bank 3 |
| Broche F2 | I/O — User I/O bank 3 |
| Broche F3 | I/O — User I/O bank 3 |
| Broche F4 | I/O — User I/O bank 3 |
| Broche F5 | GND — Ground |
| Broche F6 | VCCINT — Core supply 1.71-1.89 V |
| Broche F7 | GND — Ground |
| Broche F8 | I/O — User I/O bank 4 |
| Broche F9 | I/O — User I/O bank 4 |
| Broche F10 | I/O — User I/O bank 4 |
| Broche F11 | I/O — User I/O bank 4 |
| Broche G1 | I/O — User I/O bank 3 |
| Broche G2 | I/O — User I/O bank 3 |
| Broche G3 | I/O — User I/O bank 3 |
| Broche G4 | I/O — User I/O bank 3 |
| Broche G5 | I/O — User I/O bank 3 |
| Broche G6 | VCCIO3 — I/O bank 3 supply |
| Broche G7 | I/O — User I/O bank 4 |
| Broche G8 | I/O — User I/O bank 4 |
| Broche G9 | I/O — User I/O bank 4 |
| Broche G10 | I/O — User I/O bank 4 |
| Broche G11 | I/O — User I/O bank 4 |
| Broche H1 | I/O — User I/O bank 3 |
| Broche H2 | I/O — User I/O bank 3 |
| Broche H3 | I/O — User I/O bank 3 |
| Broche H4 | I/O — User I/O bank 3 |
| Broche H5 | I/O — User I/O bank 3 |
| Broche H6 | GND — Ground |
| Broche H7 | I/O — User I/O bank 4 |
| Broche H8 | I/O — User I/O bank 4 |
| Broche H9 | I/O — User I/O bank 4 |
| Broche H10 | I/O — User I/O bank 4 |
| Broche H11 | I/O — User I/O bank 4 |
| Broche J1 | I/O — User I/O bank 3 |
| Broche J2 | I/O — User I/O bank 3 |
| Broche J3 | I/O — User I/O bank 3 |
| Broche J4 | I/O — User I/O bank 3 |
| Broche J5 | I/O — User I/O bank 3 |
| Broche J6 | VCCIO4 — I/O bank 4 supply |
| Broche J7 | I/O — User I/O bank 4 |
| Broche J8 | I/O — User I/O bank 4 |
| Broche J9 | I/O — User I/O bank 4 |
| Broche J10 | I/O — User I/O bank 4 |
| Broche J11 | I/O — User I/O bank 4 |
| Broche K1 | I/O — User I/O bank 3 |
| Broche K2 | I/O — User I/O bank 3 |
| Broche K3 | I/O — User I/O bank 3 |
| Broche K4 | I/O — User I/O bank 3 |
| Broche K5 | GND — Ground |
| Broche K6 | VCCINT — Core supply 1.71-1.89 V |
| Broche K7 | GND — Ground |
| Broche K8 | I/O — User I/O bank 4 |
| Broche K9 | I/O — User I/O bank 4 |
| Broche K10 | I/O — User I/O bank 4 |
| Broche K11 | I/O — User I/O bank 4 |
| Broche L1 | I/O — User I/O bank 3 |
| Broche L2 | I/O — User I/O bank 3 |
| Broche L3 | I/O — User I/O bank 3 |
| Broche L4 | I/O — User I/O bank 3 |
| Broche L5 | I/O — User I/O bank 3 |
| Broche L6 | VCCIO4 — I/O bank 4 supply |
| Broche L7 | I/O — User I/O bank 4 |
| Broche L8 | I/O — User I/O bank 4 |
| Broche L9 | I/O — User I/O bank 4 |
| Broche L10 | I/O — User I/O bank 4 |
| Broche L11 | I/O — User I/O bank 4 |
| Broche M1 | I/O — User I/O bank 1 |
| Broche M2 | I/O — User I/O bank 1 |
| Broche M3 | I/O — User I/O bank 1 |
| Broche M4 | GND — Ground |
| Broche M5 | I/O — User I/O bank 1 |
| Broche M6 | nCONFIG — Configuration control (input) |
| Broche M7 | nSTATUS — Configuration status (output) |
| Broche M8 | I/O — User I/O bank 2 |
| Broche M9 | GND — Ground |
| Broche M10 | I/O — User I/O bank 2 |
| Broche M11 | I/O — User I/O bank 2 |
| Broche N1 | I/O — User I/O bank 1 |
| Broche N2 | I/O — User I/O bank 1 |
| Broche N3 | I/O — User I/O bank 1 |
| Broche N4 | VCCIO1 — I/O bank 1 supply |
| Broche N5 | I/O — User I/O bank 1 |
| Broche N6 | GND — Ground |
| Broche N7 | I/O — User I/O bank 2 |
| Broche N8 | I/O — User I/O bank 2 |
| Broche N9 | VCCIO2 — I/O bank 2 supply |
| Broche N10 | I/O — User I/O bank 2 |
| Broche N11 | I/O — User I/O bank 2 |
| Broche P1 | I/O — User I/O bank 1 |
| Broche P2 | I/O — User I/O bank 1 |
| Broche P3 | I/O — User I/O bank 1 |
| Broche P4 | I/O — User I/O bank 1 |
| Broche P5 | I/O — User I/O bank 1 |
| Broche P6 | VCCINT — Core supply 1.71-1.89 V |
| Broche P7 | I/O — User I/O bank 2 |
| Broche P8 | I/O — User I/O bank 2 |
| Broche P9 | I/O — User I/O bank 2 |
| Broche P10 | I/O — User I/O bank 2 |
| Broche P11 | I/O — User I/O bank 2 |
| Broche R1 | I/O — User I/O bank 1 |
| Broche R2 | I/O — User I/O bank 1 |
| Broche R3 | I/O — User I/O bank 1 |
| Broche R4 | I/O — User I/O bank 1 |
| Broche R5 | I/O — User I/O bank 1 |
| Broche R6 | GND — Ground |
| Broche R7 | I/O — User I/O bank 2 |
| Broche R8 | I/O — User I/O bank 2 |
| Broche R9 | I/O — User I/O bank 2 |
| Broche R10 | I/O — User I/O bank 2 |
| Broche R11 | I/O — User I/O bank 2 |
| Broche T1 | I/O — User I/O bank 1 |
| Broche T2 | I/O — User I/O bank 1 |
| Broche T3 | I/O — User I/O bank 1 |
| Broche T4 | I/O — User I/O bank 1 |
| Broche T5 | I/O — User I/O bank 1 |
| Broche T6 | CONF_DONE — Configuration done (output) |
| Broche T7 | I/O — User I/O bank 2 |
| Broche T8 | I/O — User I/O bank 2 |
| Broche T9 | I/O — User I/O bank 2 |
| Broche T10 | I/O — User I/O bank 2 |
| Broche T11 | I/O — User I/O bank 2 |
Applications typiques
EPM570GM256I5N convient pour 6 applications: Microcontroller I/O Expansion, Bus Interface Bridging, Power-Up and Power-Sequencing Controller, FPGA Configuration Manager, Board-Level Glue Logic Replacement, Legacy Industrial Control Retrofit.
Microcontroller I/O Expansion
The EPM570GM256I5N is widely used to expand the limited I/O count of 8-bit and 32-bit microcontrollers. With 160 user I/Os, 570 logic elements, and 5.4 ns propagation delay, it can decode address lines to drive peripheral chip-selects, multiplex additional key-scan or LED-scan matrices, and provide deterministic timing for real-time control loops. Unlike an FPGA, it powers up instantly without a boot PROM, so I/O signals are valid within microseconds of VCC ramp. MultiVolt I/O banks (1.5 V to 5.0 V) allow the CPLD to bridge between a 1.8 V MCU and 3.3 V peripherals without external level shifters, saving board area and BOM cost in industrial controllers and consumer appliances.
Recommandé
Bus Interface Bridging
The EPM570GM256I5N excels as a glue-logic bridge between mismatched bus protocols, such as parallel 16-bit MCU buses to 32-bit peripherals, or asynchronous SRAM to high-speed ADC/DAC interfaces. Its 440 macrocells and 5.4 ns tpd support pipelined address-latch, chip-select, and wait-state generation at clock rates beyond 150 MHz. The device's 3.3 V PCI-compatible I/O cells drive backplanes directly, while MultiVolt I/O banks allow direct connection to 1.8 V ASICs. In a typical application, the CPLD bridges a 16-bit MPU bus to a 32-bit DDR memory controller, generating burst-mode control signals with deterministic timing that ASICs cannot match.
Recommandé
Power-Up and Power-Sequencing Controller
Because the EPM570GM256I5N is non-volatile flash-based, it powers up with all outputs defined in less than 1 ms, making it ideal for power-rail sequencing in multi-rail systems. Engineers commonly program it to assert enable signals to switching regulators in a defined order, monitor PG (power-good) feedback, and hold downstream loads in reset until all rails are stable. The 5.4 ns propagation delay ensures sub-microsecond response to fault conditions, and the industrial -40 C to +100 C temperature range supports deployment in outdoor telecom, industrial automation, and automotive-grade environments where supply integrity is critical.
Recommandé
FPGA Configuration Manager
The EPM570GM256I5N is frequently used as a companion configuration manager for FPGAs that require multiple bitstreams, golden-image fallback, or field updates. The CPLD's embedded 8 Kbit User Flash Memory can store one or two compressed FPGA bitstreams, while its JTAG port chains to the FPGA for programming. With 5.4 ns timing and 160 I/Os, the device can route FPGA configuration pins, mode-select jumpers, and watchdog signals, and load the FPGA via SelectMAP or SPI in well under 100 ms. This is a common pattern in defense, aerospace, and industrial designs where deterministic FPGA bring-up is mandatory.
Recommandé
Board-Level Glue Logic Replacement
A single EPM570GM256I5N can replace dozens of 74-series TTL or CMOS discrete logic packages (gates, muxes, latches, decoders, counters) with a single 11x11 mm BGA, dramatically reducing PCB area and BOM count. With 570 LEs and 440 macrocells, the device can absorb entire legacy schematics while adding JTAG-reprogrammability that simplifies board revisions. The 5.4 ns tpd matches or beats standard 74F logic, and the industrial temperature range covers factory-floor, automotive, and outdoor installations. This consolidation also reduces EMI by eliminating long point-to-point discrete-logic traces.
Recommandé
Legacy Industrial Control Retrofit
The EPM570GM256I5N's instant-on, deterministic behavior and industrial temperature rating make it a common retrofit for legacy PLC, CNC, and motor-drive controllers that must keep operating for decades. Engineers use it to add modern interfaces (SPI to legacy parallel buses, USB to RS-232 emulation) without redesigning the host board. The flash-based non-volatile configuration survives 20+ year storage and is JTAG-reprogrammable in the field via the test header. Its 5.4 ns tpd is adequate for step/direction pulse trains up to ~50 MHz in servo drive retrofits.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM570GM256I5N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM570GM256C5N | EPM570GF256I5N | EPM570F256I5N | EPM570GM100I5N | EPM570F100I5N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 256-TFBGA (11x11 mm) | 256-TFBGA (11x11 mm) - same | 256-TFBGA (11x11 mm) - same | 256-FBGA (17x17 mm) - same family, different PCB pad | 100-MBGA - same family, different PCB pad | 100-FBGA - same family, different PCB pad |
| Logic Elements | 570 | 570 (identical die) | 570 (identical die) | 570 (identical die) | 570 (identical die) | 570 (identical die) |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| User I/Os | 160 | 160 | 160 | 212 | 76 | 100 |
| Propagation Delay (tpd) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns |
| Operating Temperature | -40 C to +100 C (industrial) | 0 C to +85 C (commercial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) |
| Core Voltage | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V |
| UFM (User Flash) | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit |
Principaux différenciateurs
- Largest I/O count in MAX II family for industrial grade (vs EPM570GM100I5N)
- Industrial temperature range with maximum pin count (vs EPM570GM256C5N)
- Smallest MBGA footprint for 160-I/O MAX II CPLD (vs EPM570F256I5N)
Notes de conception
The MAX II CPLD core requires 1.71-1.89 V (VCCINT) plus four independent VCCIO bank supplies (1.5/1.8/2.5/3.3 V). Place a 0.1 uF ceramic decoupling capacitor within 3 mm of every VCCINT pin and a 10 uF bulk tantalum or ceramic capacitor near each VCCIO bank. Total inrush current during ISP programming may briefly reach 200 mA; ensure the regulator has 500 mA headroom. For MultiVolt operation, unused I/O banks should still be powered (tie VCCIO to the lowest used voltage) to keep I/O cells in a defined state.
The 256-MBGA package uses a 1.0 mm ball pitch on an 11x11 mm substrate. Escape routing between balls requires 4 routing layers minimum with 0.1 mm trace/space; a 6-layer stack-up is recommended. Place a continuous ground plane on layer 2 directly beneath the BGA to provide a low-impedance return path for the high-edge-rate JTAG and configuration signals. Avoid running clock traces between BGA balls - route them on outer layers only after escape.
Keep JTAG signals (TCK, TMS, TDI, TDO) short (< 50 mm) and route them on the same layer to avoid stub reflections. Add a 10 kohm pull-up to TCK, TMS, and TDI per IEEE 1149.1. Series-terminate TCK with 22-33 ohm if the trace exceeds 25 mm or if multiple devices share the JTAG chain. Place a guard ring of ground vias around the BGA to reduce EMI coupling into adjacent analog sections.
Do not leave nCONFIG floating - tie it to VCCIO through a 10 kohm resistor to ensure the device enters user mode at power-up. The CONF_DONE and nSTATUS pins are open-drain during configuration and require external 10 kohm pull-ups to VCCIO. When programming in-system via JTAG, ensure the JTAG chain order in Quartus matches the physical daisy-chain (TDO of one device to TDI of the next); reversed chains will fail silently with chain-checker errors.
The 5.4 ns tpd and 160 MHz internal performance place the MAX II in the moderate-speed logic tier. Series-terminate outputs that drive traces longer than 50 mm or that fan out to more than 4 loads, using 22-33 ohm resistors at the source. For 3.3 V PCI signaling, the I/O banks must be configured for 3.3 V PCI compliance in Quartus; default LVTTL settings will not meet PCI rise/fall requirements. Avoid placing the CPLD near switching power inductors - the 8 Kbit UFM block is sensitive to EMI above 100 MHz.
Informations de conformité
Lead-free / RoHS compliant per 'N' suffix in MPN. Industrial temperature grade (I5N) but not AEC-Q100 qualified - for automotive designs contact Intel/Altera sales for AEC-Q100 status.
