EPM570GM256I5N - 570 LE MAX II CPLD, 256-MBGA | Intel (Altera)
MPN: EPM570GM256I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $39.76 | $39.76 |
| 10 | $35.5 | $355.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.8 | $12,400.00 |
| 1,000 | $21.4 | $21,400.00 |
Drop-in alternatives for EPM570GM256I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570GM256C5N
✅ Drop-In✓ In Stock
$18.6 / Unit
View Datasheet →EPM570GF256I5N
✅ Drop-In✓ In Stock
$24.1 / Unit
View Datasheet →EPM570F256I5N
✅ Drop-In✓ In Stock
$19.85 / Unit
View Datasheet →EPM570GM100I5N
✅ Drop-In✓ In Stock
$8.55 / Unit
View Datasheet →EPM570F100I5N
✅ Drop-In✓ In Stock
$13.4 / Unit
View Datasheet →EPM570GM256I5N Maximum Ratings & Electrical Characteristics
| Device Family | MAX II |
| Series | MAX II G |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| User I/Os | 160 |
| Propagation Delay (tpd) | 5.4 ns (max) |
| Internal Supply Voltage | 1.71 V to 1.89 V |
| User Flash Memory (UFM) | 8 Kbits |
| Programmable Type | In-System Programmable (ISP) |
| Operating Temperature | -40 C to +100 C (TJ, industrial) |
| Package Type | 256-TFBGA (MBGA), 11x11 mm |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free, RoHS compliant) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| Process Technology | 6-layer-metal flash CMOS |
EPM570GM256I5N Pin Configuration
| Pin A1 | I/O — User I/O bank 1 |
| Pin A2 | I/O — User I/O bank 1 |
| Pin A3 | I/O — User I/O bank 1 |
| Pin A4 | VCCIO1 — I/O bank 1 supply |
| Pin A5 | I/O — User I/O bank 1 |
| Pin A6 | GND — Ground |
| Pin A7 | I/O — User I/O bank 2 |
| Pin A8 | I/O — User I/O bank 2 |
| Pin A9 | VCCIO2 — I/O bank 2 supply |
| Pin A10 | I/O — User I/O bank 2 |
| Pin A11 | I/O — User I/O bank 2 |
| Pin B1 | I/O — User I/O bank 1 |
| Pin B2 | I/O — User I/O bank 1 |
| Pin B3 | I/O — User I/O bank 1 |
| Pin B4 | VCCINT — Core supply 1.71-1.89 V |
| Pin B5 | I/O — User I/O bank 1 |
| Pin B6 | TDI — JTAG test data in |
| Pin B7 | TMS — JTAG test mode select |
| Pin B8 | TCK — JTAG test clock |
| Pin B9 | I/O — User I/O bank 2 |
| Pin B10 | I/O — User I/O bank 2 |
| Pin B11 | I/O — User I/O bank 2 |
| Pin C1 | I/O — User I/O bank 1 |
| Pin C2 | I/O — User I/O bank 1 |
| Pin C3 | I/O — User I/O bank 1 |
| Pin C4 | I/O — User I/O bank 1 |
| Pin C5 | GND — Ground |
| Pin C6 | TDO — JTAG test data out |
| Pin C7 | I/O — User I/O bank 2 |
| Pin C8 | I/O — User I/O bank 2 |
| Pin C9 | I/O — User I/O bank 2 |
| Pin C10 | I/O — User I/O bank 2 |
| Pin C11 | I/O — User I/O bank 2 |
| Pin D1 | I/O — User I/O bank 1 |
| Pin D2 | I/O — User I/O bank 1 |
| Pin D3 | I/O — User I/O bank 1 |
| Pin D4 | I/O — User I/O bank 1 |
| Pin D5 | I/O — User I/O bank 1 |
| Pin D6 | GND — Ground |
| Pin D7 | I/O — User I/O bank 2 |
| Pin D8 | I/O — User I/O bank 2 |
| Pin D9 | I/O — User I/O bank 2 |
| Pin D10 | I/O — User I/O bank 2 |
| Pin D11 | I/O — User I/O bank 2 |
| Pin E1 | I/O — User I/O bank 3 |
| Pin E2 | I/O — User I/O bank 3 |
| Pin E3 | I/O — User I/O bank 3 |
| Pin E4 | I/O — User I/O bank 3 |
| Pin E5 | I/O — User I/O bank 3 |
| Pin E6 | VCCIO3 — I/O bank 3 supply |
| Pin E7 | I/O — User I/O bank 4 |
| Pin E8 | I/O — User I/O bank 4 |
| Pin E9 | I/O — User I/O bank 4 |
| Pin E10 | I/O — User I/O bank 4 |
| Pin E11 | I/O — User I/O bank 4 |
| Pin F1 | I/O — User I/O bank 3 |
| Pin F2 | I/O — User I/O bank 3 |
| Pin F3 | I/O — User I/O bank 3 |
| Pin F4 | I/O — User I/O bank 3 |
| Pin F5 | GND — Ground |
| Pin F6 | VCCINT — Core supply 1.71-1.89 V |
| Pin F7 | GND — Ground |
| Pin F8 | I/O — User I/O bank 4 |
| Pin F9 | I/O — User I/O bank 4 |
| Pin F10 | I/O — User I/O bank 4 |
| Pin F11 | I/O — User I/O bank 4 |
| Pin G1 | I/O — User I/O bank 3 |
| Pin G2 | I/O — User I/O bank 3 |
| Pin G3 | I/O — User I/O bank 3 |
| Pin G4 | I/O — User I/O bank 3 |
| Pin G5 | I/O — User I/O bank 3 |
| Pin G6 | VCCIO3 — I/O bank 3 supply |
| Pin G7 | I/O — User I/O bank 4 |
| Pin G8 | I/O — User I/O bank 4 |
| Pin G9 | I/O — User I/O bank 4 |
| Pin G10 | I/O — User I/O bank 4 |
| Pin G11 | I/O — User I/O bank 4 |
| Pin H1 | I/O — User I/O bank 3 |
| Pin H2 | I/O — User I/O bank 3 |
| Pin H3 | I/O — User I/O bank 3 |
| Pin H4 | I/O — User I/O bank 3 |
| Pin H5 | I/O — User I/O bank 3 |
| Pin H6 | GND — Ground |
| Pin H7 | I/O — User I/O bank 4 |
| Pin H8 | I/O — User I/O bank 4 |
| Pin H9 | I/O — User I/O bank 4 |
| Pin H10 | I/O — User I/O bank 4 |
| Pin H11 | I/O — User I/O bank 4 |
| Pin J1 | I/O — User I/O bank 3 |
| Pin J2 | I/O — User I/O bank 3 |
| Pin J3 | I/O — User I/O bank 3 |
| Pin J4 | I/O — User I/O bank 3 |
| Pin J5 | I/O — User I/O bank 3 |
| Pin J6 | VCCIO4 — I/O bank 4 supply |
| Pin J7 | I/O — User I/O bank 4 |
| Pin J8 | I/O — User I/O bank 4 |
| Pin J9 | I/O — User I/O bank 4 |
| Pin J10 | I/O — User I/O bank 4 |
| Pin J11 | I/O — User I/O bank 4 |
| Pin K1 | I/O — User I/O bank 3 |
| Pin K2 | I/O — User I/O bank 3 |
| Pin K3 | I/O — User I/O bank 3 |
| Pin K4 | I/O — User I/O bank 3 |
| Pin K5 | GND — Ground |
| Pin K6 | VCCINT — Core supply 1.71-1.89 V |
| Pin K7 | GND — Ground |
| Pin K8 | I/O — User I/O bank 4 |
| Pin K9 | I/O — User I/O bank 4 |
| Pin K10 | I/O — User I/O bank 4 |
| Pin K11 | I/O — User I/O bank 4 |
| Pin L1 | I/O — User I/O bank 3 |
| Pin L2 | I/O — User I/O bank 3 |
| Pin L3 | I/O — User I/O bank 3 |
| Pin L4 | I/O — User I/O bank 3 |
| Pin L5 | I/O — User I/O bank 3 |
| Pin L6 | VCCIO4 — I/O bank 4 supply |
| Pin L7 | I/O — User I/O bank 4 |
| Pin L8 | I/O — User I/O bank 4 |
| Pin L9 | I/O — User I/O bank 4 |
| Pin L10 | I/O — User I/O bank 4 |
| Pin L11 | I/O — User I/O bank 4 |
| Pin M1 | I/O — User I/O bank 1 |
| Pin M2 | I/O — User I/O bank 1 |
| Pin M3 | I/O — User I/O bank 1 |
| Pin M4 | GND — Ground |
| Pin M5 | I/O — User I/O bank 1 |
| Pin M6 | nCONFIG — Configuration control (input) |
| Pin M7 | nSTATUS — Configuration status (output) |
| Pin M8 | I/O — User I/O bank 2 |
| Pin M9 | GND — Ground |
| Pin M10 | I/O — User I/O bank 2 |
| Pin M11 | I/O — User I/O bank 2 |
| Pin N1 | I/O — User I/O bank 1 |
| Pin N2 | I/O — User I/O bank 1 |
| Pin N3 | I/O — User I/O bank 1 |
| Pin N4 | VCCIO1 — I/O bank 1 supply |
| Pin N5 | I/O — User I/O bank 1 |
| Pin N6 | GND — Ground |
| Pin N7 | I/O — User I/O bank 2 |
| Pin N8 | I/O — User I/O bank 2 |
| Pin N9 | VCCIO2 — I/O bank 2 supply |
| Pin N10 | I/O — User I/O bank 2 |
| Pin N11 | I/O — User I/O bank 2 |
| Pin P1 | I/O — User I/O bank 1 |
| Pin P2 | I/O — User I/O bank 1 |
| Pin P3 | I/O — User I/O bank 1 |
| Pin P4 | I/O — User I/O bank 1 |
| Pin P5 | I/O — User I/O bank 1 |
| Pin P6 | VCCINT — Core supply 1.71-1.89 V |
| Pin P7 | I/O — User I/O bank 2 |
| Pin P8 | I/O — User I/O bank 2 |
| Pin P9 | I/O — User I/O bank 2 |
| Pin P10 | I/O — User I/O bank 2 |
| Pin P11 | I/O — User I/O bank 2 |
| Pin R1 | I/O — User I/O bank 1 |
| Pin R2 | I/O — User I/O bank 1 |
| Pin R3 | I/O — User I/O bank 1 |
| Pin R4 | I/O — User I/O bank 1 |
| Pin R5 | I/O — User I/O bank 1 |
| Pin R6 | GND — Ground |
| Pin R7 | I/O — User I/O bank 2 |
| Pin R8 | I/O — User I/O bank 2 |
| Pin R9 | I/O — User I/O bank 2 |
| Pin R10 | I/O — User I/O bank 2 |
| Pin R11 | I/O — User I/O bank 2 |
| Pin T1 | I/O — User I/O bank 1 |
| Pin T2 | I/O — User I/O bank 1 |
| Pin T3 | I/O — User I/O bank 1 |
| Pin T4 | I/O — User I/O bank 1 |
| Pin T5 | I/O — User I/O bank 1 |
| Pin T6 | CONF_DONE — Configuration done (output) |
| Pin T7 | I/O — User I/O bank 2 |
| Pin T8 | I/O — User I/O bank 2 |
| Pin T9 | I/O — User I/O bank 2 |
| Pin T10 | I/O — User I/O bank 2 |
| Pin T11 | I/O — User I/O bank 2 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GM256I5N is suitable for 6 applications: Microcontroller I/O Expansion, Bus Interface Bridging, Power-Up and Power-Sequencing Controller, FPGA Configuration Manager, Board-Level Glue Logic Replacement, Legacy Industrial Control Retrofit.
Microcontroller I/O Expansion
The EPM570GM256I5N is widely used to expand the limited I/O count of 8-bit and 32-bit microcontrollers. With 160 user I/Os, 570 logic elements, and 5.4 ns propagation delay, it can decode address lines to drive peripheral chip-selects, multiplex additional key-scan or LED-scan matrices, and provide deterministic timing for real-time control loops. Unlike an FPGA, it powers up instantly without a boot PROM, so I/O signals are valid within microseconds of VCC ramp. MultiVolt I/O banks (1.5 V to 5.0 V) allow the CPLD to bridge between a 1.8 V MCU and 3.3 V peripherals without external level shifters, saving board area and BOM cost in industrial controllers and consumer appliances.
Recommended
Bus Interface Bridging
The EPM570GM256I5N excels as a glue-logic bridge between mismatched bus protocols, such as parallel 16-bit MCU buses to 32-bit peripherals, or asynchronous SRAM to high-speed ADC/DAC interfaces. Its 440 macrocells and 5.4 ns tpd support pipelined address-latch, chip-select, and wait-state generation at clock rates beyond 150 MHz. The device's 3.3 V PCI-compatible I/O cells drive backplanes directly, while MultiVolt I/O banks allow direct connection to 1.8 V ASICs. In a typical application, the CPLD bridges a 16-bit MPU bus to a 32-bit DDR memory controller, generating burst-mode control signals with deterministic timing that ASICs cannot match.
Recommended
Power-Up and Power-Sequencing Controller
Because the EPM570GM256I5N is non-volatile flash-based, it powers up with all outputs defined in less than 1 ms, making it ideal for power-rail sequencing in multi-rail systems. Engineers commonly program it to assert enable signals to switching regulators in a defined order, monitor PG (power-good) feedback, and hold downstream loads in reset until all rails are stable. The 5.4 ns propagation delay ensures sub-microsecond response to fault conditions, and the industrial -40 C to +100 C temperature range supports deployment in outdoor telecom, industrial automation, and automotive-grade environments where supply integrity is critical.
Recommended
FPGA Configuration Manager
The EPM570GM256I5N is frequently used as a companion configuration manager for FPGAs that require multiple bitstreams, golden-image fallback, or field updates. The CPLD's embedded 8 Kbit User Flash Memory can store one or two compressed FPGA bitstreams, while its JTAG port chains to the FPGA for programming. With 5.4 ns timing and 160 I/Os, the device can route FPGA configuration pins, mode-select jumpers, and watchdog signals, and load the FPGA via SelectMAP or SPI in well under 100 ms. This is a common pattern in defense, aerospace, and industrial designs where deterministic FPGA bring-up is mandatory.
Recommended
Board-Level Glue Logic Replacement
A single EPM570GM256I5N can replace dozens of 74-series TTL or CMOS discrete logic packages (gates, muxes, latches, decoders, counters) with a single 11x11 mm BGA, dramatically reducing PCB area and BOM count. With 570 LEs and 440 macrocells, the device can absorb entire legacy schematics while adding JTAG-reprogrammability that simplifies board revisions. The 5.4 ns tpd matches or beats standard 74F logic, and the industrial temperature range covers factory-floor, automotive, and outdoor installations. This consolidation also reduces EMI by eliminating long point-to-point discrete-logic traces.
Recommended
Legacy Industrial Control Retrofit
The EPM570GM256I5N's instant-on, deterministic behavior and industrial temperature rating make it a common retrofit for legacy PLC, CNC, and motor-drive controllers that must keep operating for decades. Engineers use it to add modern interfaces (SPI to legacy parallel buses, USB to RS-232 emulation) without redesigning the host board. The flash-based non-volatile configuration survives 20+ year storage and is JTAG-reprogrammable in the field via the test header. Its 5.4 ns tpd is adequate for step/direction pulse trains up to ~50 MHz in servo drive retrofits.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GM256I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GM256C5N | EPM570GF256I5N | EPM570F256I5N | EPM570GM100I5N | EPM570F100I5N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 256-TFBGA (11x11 mm) | 256-TFBGA (11x11 mm) - same | 256-TFBGA (11x11 mm) - same | 256-FBGA (17x17 mm) - same family, different PCB pad | 100-MBGA - same family, different PCB pad | 100-FBGA - same family, different PCB pad |
| Logic Elements | 570 | 570 (identical die) | 570 (identical die) | 570 (identical die) | 570 (identical die) | 570 (identical die) |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| User I/Os | 160 | 160 | 160 | 212 | 76 | 100 |
| Propagation Delay (tpd) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns |
| Operating Temperature | -40 C to +100 C (industrial) | 0 C to +85 C (commercial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) |
| Core Voltage | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V |
| UFM (User Flash) | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit |
| Unit Price (qty 1, as of 2026-09-12) | $39.76 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Largest I/O count in MAX II family for industrial grade (vs EPM570GM100I5N)
- Industrial temperature range with maximum pin count (vs EPM570GM256C5N)
- Smallest MBGA footprint for 160-I/O MAX II CPLD (vs EPM570F256I5N)
Design Notes
The MAX II CPLD core requires 1.71-1.89 V (VCCINT) plus four independent VCCIO bank supplies (1.5/1.8/2.5/3.3 V). Place a 0.1 uF ceramic decoupling capacitor within 3 mm of every VCCINT pin and a 10 uF bulk tantalum or ceramic capacitor near each VCCIO bank. Total inrush current during ISP programming may briefly reach 200 mA; ensure the regulator has 500 mA headroom. For MultiVolt operation, unused I/O banks should still be powered (tie VCCIO to the lowest used voltage) to keep I/O cells in a defined state.
The 256-MBGA package uses a 1.0 mm ball pitch on an 11x11 mm substrate. Escape routing between balls requires 4 routing layers minimum with 0.1 mm trace/space; a 6-layer stack-up is recommended. Place a continuous ground plane on layer 2 directly beneath the BGA to provide a low-impedance return path for the high-edge-rate JTAG and configuration signals. Avoid running clock traces between BGA balls - route them on outer layers only after escape.
Keep JTAG signals (TCK, TMS, TDI, TDO) short (< 50 mm) and route them on the same layer to avoid stub reflections. Add a 10 kohm pull-up to TCK, TMS, and TDI per IEEE 1149.1. Series-terminate TCK with 22-33 ohm if the trace exceeds 25 mm or if multiple devices share the JTAG chain. Place a guard ring of ground vias around the BGA to reduce EMI coupling into adjacent analog sections.
Do not leave nCONFIG floating - tie it to VCCIO through a 10 kohm resistor to ensure the device enters user mode at power-up. The CONF_DONE and nSTATUS pins are open-drain during configuration and require external 10 kohm pull-ups to VCCIO. When programming in-system via JTAG, ensure the JTAG chain order in Quartus matches the physical daisy-chain (TDO of one device to TDI of the next); reversed chains will fail silently with chain-checker errors.
The 5.4 ns tpd and 160 MHz internal performance place the MAX II in the moderate-speed logic tier. Series-terminate outputs that drive traces longer than 50 mm or that fan out to more than 4 loads, using 22-33 ohm resistors at the source. For 3.3 V PCI signaling, the I/O banks must be configured for 3.3 V PCI compliance in Quartus; default LVTTL settings will not meet PCI rise/fall requirements. Avoid placing the CPLD near switching power inductors - the 8 Kbit UFM block is sensitive to EMI above 100 MHz.
Compliance Information
Lead-free / RoHS compliant per 'N' suffix in MPN. Industrial temperature grade (I5N) but not AEC-Q100 qualified - for automotive designs contact Intel/Altera sales for AEC-Q100 status.
