EPM7128ELC84-10 - 128-Macrocell CPLD, 10ns, 5V, 84-PLCC | Intel
MPN: EPM7128ELC84-10 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.45 | $4,225.00 |
| 1,000 | $7.2 | $7,200.00 |
Drop-in alternatives for EPM7128ELC84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128ELC84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ELC84-12
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEPM7128SLC84-10
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM7128AELC84-10N
β Drop-Inβ In Stock
$10.45 / Unit
View Datasheet βEPM7128ELC84-20
β Drop-Inβ In Stock
$24.2 / Unit
View Datasheet βEPM7128SLC84-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ELC84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| User I/Os | 68 |
| Dedicated Inputs | 12 |
| Operating Voltage (VCCINT/VCClO) | 5 V |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Package | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Socket |
| Operating Temperature | 0C to +70C (Commercial) |
| Technology | EEPROM-based CMOS |
| Programming Interface | IEEE 1149.1 (JTAG) ISP |
| In-System Programmable | Yes |
EPM7128ELC84-10 Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | I/O β User I/O (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O (bank 2) |
| Pin 14 | I/O β User I/O (bank 2) |
| Pin 15 | I/O β User I/O (bank 2) |
| Pin 16 | I/O β User I/O (bank 2) |
| Pin 17 | I/O β User I/O (bank 2) |
| Pin 18 | I/O β User I/O (bank 2) |
| Pin 19 | I/O β User I/O (bank 2) |
| Pin 20 | I/O β User I/O (bank 2) |
| Pin 21 | I/O β User I/O (bank 2) |
| Pin 22 | I/O β User I/O (bank 2) |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | GND β Ground |
| Pin 25 | TDI β JTAG Test Data In |
| Pin 26 | TMS β JTAG Test Mode Select |
| Pin 27 | TCK β JTAG Test Clock |
| Pin 28 | I/O β User I/O (bank 2) |
| Pin 29 | I/O β User I/O (bank 2) |
| Pin 30 | I/O β User I/O (bank 2) |
| Pin 31 | I/O β User I/O (bank 3) |
| Pin 32 | I/O β User I/O (bank 3) |
| Pin 33 | I/O β User I/O (bank 3) |
| Pin 34 | I/O β User I/O (bank 3) |
| Pin 35 | I/O β User I/O (bank 3) |
| Pin 36 | I/O β User I/O (bank 3) |
| Pin 37 | VCC β 5V supply |
| Pin 38 | I/O β User I/O (bank 3) |
| Pin 39 | I/O β User I/O (bank 3) |
| Pin 40 | I/O β User I/O (bank 3) |
| Pin 41 | I/O β User I/O (bank 3) |
| Pin 42 | INPUT/GCLK β Dedicated input / global clock |
| Pin 43 | INPUT/OE1 β Dedicated input / Output Enable 1 |
| Pin 44 | INPUT/OE2/GCLK2 β Dedicated input / Output Enable 2 / global clock 2 |
| Pin 45 | INPUT/CLR β Dedicated input / Clear |
| Pin 46 | I/O β User I/O (bank 4) |
| Pin 47 | I/O β User I/O (bank 4) |
| Pin 48 | I/O β User I/O (bank 4) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O (bank 4) |
| Pin 51 | I/O β User I/O (bank 4) |
| Pin 52 | I/O β User I/O (bank 4) |
| Pin 53 | I/O β User I/O (bank 4) |
| Pin 54 | I/O β User I/O (bank 4) |
| Pin 55 | I/O β User I/O (bank 4) |
| Pin 56 | I/O β User I/O (bank 4) |
| Pin 57 | I/O β User I/O (bank 4) |
| Pin 58 | I/O β User I/O (bank 4) |
| Pin 59 | I/O β User I/O (bank 4) |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O (bank 4) |
| Pin 62 | I/O β User I/O (bank 4) |
| Pin 63 | I/O β User I/O (bank 1) |
| Pin 64 | I/O β User I/O (bank 1) |
| Pin 65 | I/O β User I/O (bank 1) |
| Pin 66 | I/O β User I/O (bank 1) |
| Pin 67 | I/O β User I/O (bank 1) |
| Pin 68 | VCC β 5V supply |
| Pin 69 | I/O β User I/O (bank 1) |
| Pin 70 | I/O β User I/O (bank 1) |
| Pin 71 | I/O β User I/O (bank 1) |
| Pin 72 | I/O β User I/O (bank 1) |
| Pin 73 | I/O β User I/O (bank 1) |
| Pin 74 | I/O β User I/O (bank 1) |
| Pin 75 | TDO β JTAG Test Data Out |
| Pin 76 | GND β Ground |
| Pin 77 | INPUT β Dedicated input (bank 1) |
| Pin 78 | INPUT β Dedicated input (bank 1) |
| Pin 79 | INPUT β Dedicated input (bank 1) |
| Pin 80 | INPUT β Dedicated input (bank 1) |
| Pin 81 | INPUT β Dedicated input (bank 1) |
| Pin 82 | INPUT β Dedicated input (bank 1) |
| Pin 83 | INPUT β Dedicated input (bank 1) |
| Pin 84 | INPUT β Dedicated input (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ELC84-10 is suitable for 6 applications: Microprocessor Address Decoding, Bus Interface Bridging, State Machine Control Logic, Legacy Industrial Glue Logic Replacement, Industrial Control I/O Expansion, Communication Protocol Bridging.
Microprocessor Address Decoding
The EPM7128ELC84-10 fits microprocessor address decoding because its 128 macrocells and 68 user I/Os provide ample logic capacity for full 24-bit or 32-bit address map decoding, while its 10ns tPD adds minimal wait-state insertion on most modern 5V microcontrollers and DSPs. Its non-volatile EEPROM means decoding logic is available instantly on power-up with no boot PROM, simplifying board bring-up. Place the part between the processor and the memory/peripheral bus; each macrocell can implement one chip-select or enable line. Compared to discrete 74-series glue logic, the EPM7128ELC84-10 consolidates dozens of packages into one, reducing board area and improving signal integrity by shortening address decode paths.
Recommended
Bus Interface Bridging
The EPM7128ELC84-10 is well suited to bus interface bridging between mismatched widths or voltage standards, since its 5V-tolerant I/Os can directly drive 5V peripherals while its macrocell logic can re-time data across an 8-bit-to-16-bit or 16-bit-to-32-bit boundary. The 10ns pin-to-pin delay keeps bridging latency low, allowing glue between two clock domains at moderate bus frequencies (up to roughly 50 MHz). The non-volatile configuration simplifies in-field firmware updates via JTAG without external boot storage. Use it to consolidate handshake logic, parity generation, or wait-state insertion that would otherwise require several discrete packages.
Recommended
State Machine Control Logic
Implementing state machines in the EPM7128ELC84-10 leverages the deterministic single-cycle propagation delay of the MAX 7000 PIA architecture, giving engineers predictable state-transition timing without FPGA fabric overhead. With 128 macrocells, the device can host multiple parallel state machines (e.g., a UART controller, an I/O sequencer, and a watchdog timer) in one chip. The 68 user I/Os comfortably accommodate status LEDs, control outputs, and sensor inputs. The 5V I/O compatibility allows direct interface with industrial sensors and 5V actuator drivers without level shifters. JTAG-based in-system programmability enables on-line state-machine tuning during development without re-spinning the board.
Recommended
Legacy Industrial Glue Logic Replacement
The EPM7128ELC84-10 is widely used to replace aging 74HC/74LS glue logic in legacy industrial controllers, where a single CPLD can replace 5 to 20 discrete packages, freeing board area and reducing power consumption. Its 5V tolerance matches the legacy supply rail and 5V peripherals, eliminating the level-shifters that would be required with newer 3.3V-only parts. The 84-pin PLCC socket-compatible package allows direct drop-in retrofit of older PLCC sockets that previously held legacy decode PLDs. The non-volatile EEPROM eliminates battery-backed configuration or external PROMs required by older architectures, increasing long-term reliability.
Recommended
Industrial Control I/O Expansion
In PLC-style industrial controllers, the EPM7128ELC84-10 serves as the I/O expansion and conditioning stage, providing 68 user I/Os that can be software-defined as inputs, outputs, or bidirectional signals via JTAG programming. The 5V I/O tolerance interfaces directly with 24V-tolerant opto-isolated input modules via external resistor dividers, and 5V logic outputs can drive relays, solenoids, and LED indicators. The 10ns tPD supports real-time control loops up to a few kHz, sufficient for slow-loop process control and discrete I/O scanning. EEPROM-based configuration means field updates can be made via JTAG without removing the part.
Recommended
Communication Protocol Bridging
The EPM7128ELC84-10 is frequently deployed as a low-cost protocol-bridging device, converting between legacy parallel buses (e.g., 8-bit ISA, 16-bit memory-mapped I/O) and serial protocols (UART, SPI, I2C) at speeds up to roughly 50 MHz. Its 128 macrocells can implement the full state machine for a UART/SPI bridge plus FIFO buffer management, and 68 I/Os allow simultaneous parallel-bus and serial-peripheral connections. The deterministic 10ns timing ensures glitch-free protocol handshakes. In-system programmability via JTAG allows firmware updates during commissioning or field service. The 5V tolerance simplifies integration with legacy 5V bus systems common in industrial and telecom hardware.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ELC84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128ELC84-15 | EPM7128ELC84-12 | EPM7128SLC84-10 | EPM7128AELC84-10N | EPM7128ELC84-20 | EPM7128SLC84-15N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Operating Voltage | 5V (E-suffix) | 5V (E-suffix) | 5V (E-suffix) | 5V (S-suffix) | 3.3V (A-suffix) | 5V (E-suffix) | 5V (S-suffix) |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns | 12 ns | 10 ns | 10 ns | 20 ns | 15 ns |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 |
| In-System Programmable | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Technology | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS | EEPROM CMOS |
Key Differentiators
- Standard commercial speed grade (-10) balances speed and availability (vs EPM7128ELC84-15)
- E-suffix 5V operation matches legacy 5V system rails (vs EPM7128AELC84-10N)
- Non-volatile EEPROM means instant-on with no boot PROM (vs EPM7128ELC84-15)
Design Notes
Do NOT confuse the E-suffix (EPM7128ELC84-10, 5V) with the A-suffix (EPM7128AELC84-10, 3.3V) - they share the same 84-pin PLCC footprint but are not electrically interchangeable. According to the MAX 7000 datasheet family, applying 5V to an A-suffix part will damage the device, and applying 3.3V to an E-suffix part may not meet VIH thresholds reliably. Always verify the supply voltage before substituting.
The 84-pin PLCC package is socket-compatible and can be installed in a PLCC socket for easy field replacement. According to the MAX 7000 datasheet, place decoupling capacitors (0.1uF ceramic) close to each VCC pin (typically pins 37, 68) and each GND pin (12, 24, 49, 60, 76) to minimize switching noise on the internal logic and JTAG interface. A bulk 10uF tantalum or ceramic capacitor on the VCC rail near the part is recommended.
For designs switching high-frequency signals (above 50 MHz), keep critical clock and JTAG traces short and impedance-controlled. According to the MAX 7000 datasheet, the JTAG pins (TCK, TMS, TDI, TDO at pins 27, 26, 25, 75) should be routed with care to avoid noise coupling during in-system programming. Series termination (33-68 ohm) on long output traces can reduce undershoot/ringing when driving capacitive loads.
Estimated: at 5V VCC, the EPM7128ELC84-10 commercial-grade part dissipates approximately 500 mW to 1 W depending on switching activity and toggle rate. The 84-pin PLCC package has a thermal resistance of roughly 35-45 C/W (theta_JA) in still air, giving a junction temperature rise of 18-45 C above ambient - well within the 0C to +70C commercial range. For industrial-temperature applications (-40C to +85C), use an I-suffix part such as EPM7128ELC84-10I if available.
Compliance Information
RoHS/REACH compliance status was not present in the verified web data; legacy CPLD parts from the MAX 7000 family vary by date code and specific part suffix - confirm RoHS compliance with the distributor at the time of purchase. AEC-Q100 is not applicable as the part is commercial-grade.
