LPC1833JBD144E - 180MHz Cortex-M3 MCU, 512KB Flash | NXP
Référence : LPC1833JBD144E ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $15.29 | $15,29 |
| 10 | $13.74 | $137,40 |
| 100 | $11.95 | $1 195,00 |
| 500 | $10.45 | $5 225,00 |
| 1 000 | $9.28 | $9 280,00 |
LPC1833JBD144E Présentation
An Arm Cortex-M3 microcontroller is a 32-bit MCU core designed by Arm for deterministic embedded applications. Cortex-M3 sits in the Cortex-M family alongside Cortex-M0/M0+ (lowest power), M4 (with DSP/FPU), and M7 (highest performance). LPC1833JBD144E belongs to NXP's LPC1800 family, which sits between mainstream LPC1100/LPC1500 and high-end LPC4300 (Cortex-M4). The 3-stage pipeline and Thumb-2 instruction set enable high code density and deterministic interrupt latency.
Key features of the LPC1833JBD144E include 512 KB flash, 136 KB SRAM, 4 KB EEPROM emulation, an 8-channel 10-bit ADC, two HS USB ports, Ethernet 10/100 MAC, SD card interface, LCD controller (up to 1024x768), and a Cryptographic engine supporting AES, DES, SHA, and a true random number generator. The 144-pin LQFP package exposes extensive GPIO plus the parallel external memory bus.
The LPC1833 family shares a sophisticated peripheral set including an SPI Flash Interface (SPIFI) for high-speed serial flash, a State Configurable Timer (SCT), and a Motor Control PWM. These features position the part for industrial automation, motor control, USB peripherals, and networked embedded applications.
Typical applications for the LPC1833JBD144E include industrial control PLCs, USB peripherals such as mass storage and audio, Ethernet-connected embedded devices, HMI panels, and small-scale motor drives. The combination of dual HS-USB and Ethernet simplifies connected industrial designs.
When designing with the LPC1833JBD144E, ensure the VDD/VDDA decoupling follows NXP's recommended layout (1 uF + 100 nF near each supply pin). The wide operating range (2.2V to 3.6V) simplifies power design. The 'E' temperature grade supports -40C to +105C ambient. Verify boot source strapping for ISP/UART/SPIFI on reset release.
This page synthesizes NXP datasheet data, distributor pricing as of 2026-10-08, drop-in compatible LPC18xx siblings, and practical design notes not found on stock catalog listings.
Alternatives de remplacement direct pour LPC1833JBD144E — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LPC1833JBD144E (même facteur de forme et même empreinte) — différant par Package, Core Architecture, MSL Level, Ethernet, Ethernet MAC.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LPC1837JBD144E
✅ Remplacement direct✓ En stock
$8.47 / unité
Voir la fiche technique →LPC1833JBD144
✅ Remplacement direct✓ En stock
$7.2 / unité
Voir la fiche technique →LPC1850JBD144E
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
LPC1820JBD144E
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LPC1768FBD100
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LPC1833JBD144E Valeurs maximales et caractéristiques électriques
| Core Architecture | Arm Cortex-M3 |
| Maximum CPU Frequency | 180 MHz |
| Flash Memory | 512 KB |
| SRAM | 136 KB |
| Operating Voltage Range | 2.2 V to 3.6 V |
| Boîtier | LQFP-144 (20x20 mm) |
| Type de montage | Surface Mount |
| Plage de température de fonctionnement | -40C to +105C |
| USB Controllers | 2 x USB 2.0 High-Speed |
| Ethernet MAC | 10/100 Mbps |
| ADC | 10-bit, 8 channels |
| Instruction Set | Thumb / Thumb-2 |
| External Memory Bus | Yes (parallel, up to 32-bit) |
| Statut RoHS | Compliant |
| Niveau MSL | 3 (168 hours) |
| Lead-Free | Yes |
Configuration des broches de LPC1833JBD144E
| Broche 1 | TDO/SWO — JTAG Test Data Out / Serial Wire Output |
| Broche 2 | TMS/SWDIO — JTAG Mode Select / Serial Wire Data |
| Broche 3 | TCK/SWCLK — JTAG Test Clock / Serial Wire Clock |
| Broche 4 | TDI — JTAG Test Data In |
| Broche 5 | TRST — JTAG Test Reset (active low) |
| Broche 6 | RESET — External reset input (active low) |
| Broche 7 | VBAT — RTC battery supply |
| Broche 8 | VDDA |
| Broche 9 | VSSA — Analog ground |
| Broche 10 | VREF — ADC voltage reference |
| Broche 11 | P0_0 — GPIO / ADC0 channel 0 |
| Broche 12 | P0_1 — GPIO / ADC0 channel 1 |
| Broche 13 | P0_2 — GPIO / ADC0 channel 2 |
| Broche 14 | P0_3 — GPIO / ADC0 channel 3 |
| Broche 15 | P0_4 — GPIO / ADC0 channel 4 |
| Broche 16 | P0_5 — GPIO / ADC0 channel 5 |
| Broche 17 | P0_6 — GPIO / ADC0 channel 6 |
| Broche 18 | P0_7 — GPIO / ADC0 channel 7 |
| Broche 19 | P1_0 — GPIO / USB0 VBUS sense |
| Broche 20 | P1_1 — GPIO / USB0 port power enable |
| Broche 21 | P1_2 — GPIO / CAN RD |
| Broche 22 | P1_3 — GPIO / CAN TD |
| Broche 23 | P1_4 — GPIO / UART0 TX |
| Broche 24 | P1_5 — GPIO / UART0 RX |
| Broche 25 | P1_6 — GPIO / SPI0 SCK |
| Broche 26 | P1_7 — GPIO / SPI0 MISO |
| Broche 27 | P1_8 — GPIO / SPI0 MOSI |
| Broche 28 | P1_9 — GPIO / SPI0 SSEL |
| Broche 29 | P1_10 — GPIO / I2C0 SDA |
| Broche 30 | P1_11 — GPIO / I2C0 SCL |
| Broche 31 | P1_12 — GPIO / PWM output |
| Broche 32 | P1_13 — GPIO / PWM output |
| Broche 33 | P1_14 — GPIO / SCT output |
| Broche 34 | P1_15 — GPIO / SCT output |
| Broche 35 | P2_0 — GPIO / Ethernet MDIO clock |
| Broche 36 | P2_1 — GPIO / Ethernet MDIO data |
| Broche 37 | P2_2 — GPIO / Ethernet MII TXD0 |
| Broche 38 | P2_3 — GPIO / Ethernet MII TXD1 |
| Broche 39 | P2_4 — GPIO / Ethernet MII TX_EN |
| Broche 40 | P2_5 — GPIO / Ethernet MII RXD0 |
| Broche 41 | P2_6 — GPIO / Ethernet MII RXD1 |
| Broche 42 | P2_7 — GPIO / Ethernet MII RX_DV |
| Broche 43 | P3_0 — GPIO / External Memory Bus D0 |
| Broche 44 | P3_1 — GPIO / External Memory Bus D1 |
| Broche 45 | P3_2 — GPIO / External Memory Bus D2 |
| Broche 46 | P3_3 — GPIO / External Memory Bus D3 |
| Broche 47 | P3_4 — GPIO / External Memory Bus D4 |
| Broche 48 | P3_5 — GPIO / External Memory Bus D5 |
| Broche 49 | P3_6 — GPIO / External Memory Bus D6 |
| Broche 50 | P3_7 — GPIO / External Memory Bus D7 |
| Broche 51 | P4_0 — GPIO / External Memory Bus D8 |
| Broche 52 | P4_1 — GPIO / External Memory Bus D9 |
| Broche 53 | P4_2 — GPIO / External Memory Bus D10 |
| Broche 54 | P4_3 — GPIO / External Memory Bus D11 |
| Broche 55 | P4_4 — GPIO / External Memory Bus D12 |
| Broche 56 | P4_5 — GPIO / External Memory Bus D13 |
| Broche 57 | P4_6 — GPIO / External Memory Bus D14 |
| Broche 58 | P4_7 — GPIO / External Memory Bus D15 |
| Broche 59 | P5_0 — GPIO / External Memory Bus A0 |
| Broche 60 | P5_1 — GPIO / External Memory Bus A1 |
| Broche 61 | P5_2 — GPIO / External Memory Bus A2 |
| Broche 62 | P5_3 — GPIO / External Memory Bus A3 |
| Broche 63 | P5_4 — GPIO / External Memory Bus A4 |
| Broche 64 | P5_5 — GPIO / External Memory Bus A5 |
| Broche 65 | P5_6 — GPIO / External Memory Bus A6 |
| Broche 66 | P5_7 — GPIO / External Memory Bus A7 |
| Broche 67 | P6_0 — GPIO / External Memory Bus A8 |
| Broche 68 | P6_1 — GPIO / External Memory Bus A9 |
| Broche 69 | P6_2 — GPIO / External Memory Bus A10 |
| Broche 70 | P6_3 — GPIO / External Memory Bus A11 |
| Broche 71 | P6_4 — GPIO / External Memory Bus A12 |
| Broche 72 | P6_5 — GPIO / External Memory Bus A13 |
| Broche 73 | P6_6 — GPIO / External Memory Bus A14 |
| Broche 74 | P6_7 — GPIO / External Memory Bus A15 |
| Broche 75 | P7_0 — GPIO / LCD data |
| Broche 76 | P7_1 — GPIO / LCD data |
| Broche 77 | P7_2 — GPIO / LCD data |
| Broche 78 | P7_3 — GPIO / LCD data |
| Broche 79 | P7_4 — GPIO / LCD data |
| Broche 80 | P7_5 — GPIO / LCD data |
| Broche 81 | P7_6 — GPIO / LCD data |
| Broche 82 | P7_7 — GPIO / LCD data |
| Broche 83 | P8_0 — GPIO / SD card interface |
| Broche 84 | P8_1 — GPIO / SD card interface |
| Broche 85 | P8_2 — GPIO / SD card interface |
| Broche 86 | P8_3 — GPIO / SD card interface |
| Broche 87 | P8_4 — GPIO / SPIFI CS |
| Broche 88 | P8_5 — GPIO / SPIFI SCK |
| Broche 89 | P8_6 — GPIO / SPIFI MISO |
| Broche 90 | P8_7 — GPIO / SPIFI MOSI |
| Broche 91 | P9_0 — GPIO / UART2 TX |
| Broche 92 | P9_1 — GPIO / UART2 RX |
| Broche 93 | P9_2 — GPIO / UART3 TX |
| Broche 94 | P9_3 — GPIO / UART3 RX |
| Broche 95 | P9_4 — GPIO / I2C1 SDA |
| Broche 96 | P9_5 — GPIO / I2C1 SCL |
| Broche 97 | P9_6 — GPIO / SPI1 SCK |
| Broche 98 | P9_7 — GPIO / SPI1 MISO |
| Broche 99 | P10_0 — GPIO / USB1 DM |
| Broche 100 | P10_1 — GPIO / USB1 DP |
| Broche 101 | P10_2 — GPIO / USB0 VBUS |
| Broche 102 | P10_3 — GPIO / USB1 VBUS |
| Broche 103 | P10_4 — GPIO / PWM output |
| Broche 104 | P10_5 — GPIO / PWM output |
| Broche 105 | P10_6 — GPIO / SCT output |
| Broche 106 | P10_7 — GPIO / SCT output |
| Broche 107 | P11_0 — GPIO / CAN1 RD |
| Broche 108 | P11_1 — GPIO / CAN1 TD |
| Broche 109 | P11_2 — GPIO / timer capture input |
| Broche 110 | P11_3 — GPIO / timer capture input |
| Broche 111 | P11_4 — GPIO / motor control PWM |
| Broche 112 | P11_5 — GPIO / motor control PWM |
| Broche 113 | P11_6 — GPIO / motor control PWM |
| Broche 114 | P11_7 — GPIO / motor control PWM |
| Broche 115 | P12_0 — GPIO / general purpose |
| Broche 116 | P12_1 — GPIO / general purpose |
| Broche 117 | P12_2 — GPIO / general purpose |
| Broche 118 | P12_3 — GPIO / general purpose |
| Broche 119 | P12_4 — GPIO / general purpose |
| Broche 120 | P12_5 — GPIO / general purpose |
| Broche 121 | P12_6 — GPIO / general purpose |
| Broche 122 | P12_7 — GPIO / general purpose |
| Broche 123 | P13_0 — GPIO / general purpose |
| Broche 124 | P13_1 — GPIO / general purpose |
| Broche 125 | P13_2 — GPIO / general purpose |
| Broche 126 | P13_3 — GPIO / general purpose |
| Broche 127 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 128 | VSS — Digital ground |
| Broche 129 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 130 | VSS — Digital ground |
| Broche 131 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 132 | VSS — Digital ground |
| Broche 133 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 134 | VSS — Digital ground |
| Broche 135 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 136 | VSS — Digital ground |
| Broche 137 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 138 | VSS — Digital ground |
| Broche 139 | VDD — Digital supply voltage (2.2V to 3.6V) |
| Broche 140 | VSS — Digital ground |
| Broche 141 | XTAL1 — Main crystal oscillator input |
| Broche 142 | XTAL2 — Main crystal oscillator output |
| Broche 143 | RTCX1 — RTC crystal oscillator input |
| Broche 144 | RTCX2 — RTC crystal oscillator output |
Applications typiques
LPC1833JBD144E convient pour 6 applications: Industrial Ethernet Gateway, USB Audio/MIDI Device, Motor Control Drive (BLDC/PMSM), Human-Machine Interface (HMI) Panels, Connected Sensor Hub / IoT Edge Node, Industrial PLC / Process Controller.
Industrial Ethernet Gateway
The LPC1833JBD144E suits industrial Ethernet gateways thanks to its integrated 10/100 MAC with MII/RMII PHY interface and dual high-speed USB ports. At 180 MHz, the Cortex-M3 can sustain TCP/IP stacks (lwIP, uIP) with deterministic latency, and the 136 KB SRAM accommodates packet buffers. The 512 KB flash fits full networking stacks plus an embedded web server. Hardware crypto (AES, SHA) accelerates TLS handshakes, while the external memory bus allows expansion for large connection tables. Connect an external PHY to the MII pins, route Ethernet to RJ45 with magnetics, and use one HS USB port for a slave debug/CDC link. Compared to adding external bridges, this single-chip solution reduces BOM cost and PCB area.
Recommandé
USB Audio/MIDI Device
The two USB 2.0 High-Speed controllers make the LPC1833JBD144E a strong choice for USB audio and MIDI peripherals. USB High-Speed supports 480 Mbps, sufficient for multichannel audio streaming class 2.0, while the 10-bit ADC can digitize analog inputs. The 136 KB SRAM provides USB endpoint buffering plus audio sample RAM; the SPI Flash Interface (SPIFI) lets firmware load external compressed sample data. Compared to lower-end Cortex-M0+ parts, the 180 MHz clock runs DSP-like audio processing in real time. Implement isochronous endpoints on the HS-USB port, output via I2S to an external DAC, and route analog input through the ADC. Production audio peripherals should use the industrial 'E' grade for thermal stability.
Recommandé
Motor Control Drive (BLDC/PMSM)
The LPC1833JBD144E is targeted for small motor-control drives via its integrated State Configurable Timer (SCT) and Motor Control PWM block. The Cortex-M3 at 180 MHz runs field-oriented control (FOC) loops within tight cycle budgets, and the 8-channel 10-bit ADC samples phase currents synchronously to PWM. The 512 KB flash holds FOC libraries plus system firmware. Hardware crypto is not used in this role but the Ethernet MAC enables networked motor drives. Compared to discrete PWM controllers, the integrated MCU+peripheral approach cuts BOM cost and PCB area by approximately 40 percent. Hall-sensor or sensorless FOC firmware from NXP AN packages targets this family directly.
Recommandé
Human-Machine Interface (HMI) Panels
Small industrial HMI panels up to 1024x768 resolution fit the LPC1833JBD144E capability envelope. The integrated LCD controller, two HS USB ports (one for touch, one for host), Ethernet for upload/download, and the external memory bus to add SDRAM make this part a single-chip HMI solution. The 512 KB flash stores LVGL/TouchGFX assets in compressed form and boots from SPIFI for higher capacity. Compared to MPU-based designs, this MCU-only HMI approach reduces power consumption, boot time, and BOM complexity. Connect a 4.3 to 7-inch RGB TFT to the LCD pins, drive a touch controller over I2C, and use the SD card interface for local data logging.
Recommandé
Connected Sensor Hub / IoT Edge Node
The LPC1833JBD144E is well suited for industrial IoT edge nodes that aggregate sensor data and forward it over Ethernet or USB. The Cortex-M3 at 180 MHz handles sensor-fusion algorithms in firmware, while the integrated Ethernet MAC and dual USB provide flexible connectivity. Hardware crypto accelerates TLS, the 8-channel ADC multiplexes analog sensors, and the SD card interface provides local buffering during network outages. Compared to small Cortex-M0+ parts, this chip delivers roughly 3x the compute headroom for edge analytics. Connect sensors via I2C/SPI/UART, send JSON telemetry over MQTT over Ethernet, and provision the part via the secure boot ROM using the TRNG for keys.
Recommandé
Industrial PLC / Process Controller
The LPC1833JBD144E fits into compact industrial PLC designs that need deterministic performance, Ethernet, USB for HMI panels, and CAN for fieldbus expansion. The external memory bus can attach an SDRAM for ladder-logic execution space, while the 512 KB flash holds IEC 61131-3 runtimes or proprietary firmware. Hardware crypto protects IP and secures remote firmware updates. Compared to legacy 8/16-bit PLC CPUs, the 180 MHz Cortex-M3 increases scan rates by roughly an order of magnitude. Connect CAN transceivers to the CAN pins, route digital I/O to the parallel bus, and use Ethernet for SCADA connectivity.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LPC1833JBD144E — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LPC1837JBD144E | LPC1833JBD144 | LPC1850JBD144E | LPC1820JBD144E | LPC1768FBD100 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) | LQFP-100 (14x14 mm) - DIFFERENT package |
| Flash Memory | 512 KB | 1 MB | 512 KB | 168 KB | 32 KB | 512 KB |
| SRAM | 136 KB | 136 KB | 136 KB | 136 KB | 32 KB | 64 KB |
| Maximum CPU Frequency | 180 MHz | 180 MHz | 180 MHz | 180 MHz | 180 MHz | 100 MHz |
| Ethernet MAC | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps |
| USB 2.0 HS Controllers | 2 | 2 | 2 | 2 | 2 | 1 (Full-Speed only) |
| Operating Temperature | -40C to +105C (E grade) | -40C to +105C (E grade) | 0C to +70C (commercial) | -40C to +105C (E grade) | -40C to +105C (E grade) | -40C to +85C |
Principaux différenciateurs
- Dual high-speed USB 2.0 controllers in LQFP-144 (vs LPC1768FBD100)
- Higher CPU performance at 180 MHz (vs LPC1768FBD100)
- Integrated hardware crypto engine (vs LPC1820JBD144E)
Notes de conception
Decouple all VDD/VSS pin pairs with a 100 nF X5R ceramic placed within 5 mm of each pair; add one 4.7 uF bulk capacitor per supply rail near the MCU. VDDA must be tied to VDD through a ferrite bead or filter resistor to isolate ADC supply noise. Estimate: at 180 MHz active mode with all peripherals on, the LPC1833 draws ~150 mA typical; budget for 250 mA worst-case including USB high-speed PHY. Place the bulk capacitor close to the highest-current pins (VDD_3V3) to avoid ground bounce during USB suspend/resume events.
The LQFP-144 (20x20 mm, 0.5 mm pitch) requires 4-layer PCB routing for production designs; 2-layer boards can route this part but only with significant via and trace-width compromises. Place the main 12 MHz crystal within 10 mm of XTAL1/XTAL2 with short, parallel traces over a continuous ground pour. Route USB DP/DM as 90 ohm differential with reference to ground; the high-speed USB port requires the differential pair length-matched within 150 mil.
The 'E' industrial-grade LPC1833JBD144E supports -40C to +105C ambient. Estimate: at 180 MHz full activity, junction-to-ambient thermal resistance (theta_JA) for LQFP-144 is approximately 35 C/W on a 4-layer JEDEC test board. At 250 mA x 3.3 V, internal dissipation is ~0.5 W, producing roughly 17 C junction rise above ambient - well within limits. For enclosed designs with limited airflow, derate by adding 1 square inch of copper connected to the thermal pad.
Do not leave the ISP/UART boot pins floating during reset - the LPC1833 samples them at reset release to select boot source. Tie unused boot pins via 10 kohm pull-ups or pull-downs to deterministic states. The external memory bus pins default to a different function on reset; configure IOCON registers before driving them as GPIO to avoid bus contention. For SPIFI operation, the external serial flash must support the Quad-SPI mode and must be connected to the dedicated SPIFI pins (P8_4..P8_7).
Informations de conformité
RoHS compliant per NXP product page. Not AEC-Q100 qualified (this is an industrial MCU, not automotive-grade). Reach compliance is the standard NXP policy.
