Xilinx

XC3090L-125PC84C - 5K-Gate FPGA, 125MHz, 84-Pin PLCC | Xilinx

Référence : XC3090L-125PC84C ✗ Fin de vie

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3.0 V to 3.6 V (typical 3.3 V) Vdss 84-pin PLCC (J-lead, package code QCCJ) Package 125 MHz Speed

À partir de $64 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$95	$95,00
10	$88	$880,00
100	$79	$7 900,00
500	$71	$35 500,00
1 000	$64	$64 000,00

ℹ️ Tous les prix sont en USD

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XC3090L-125PC84C Présentation

The Xilinx XC3090L-125PC84C is a CMOS Field Programmable Gate Array (FPGA) from the XC3000L low-voltage Logic Cell Array family, supplied in an 84-pin PLCC package. It features 320 Configurable Logic Blocks (CLBs), approximately 5000 equivalent logic gates, 928 flip-flops, and a maximum clock frequency of 125 MHz. The device operates from a 3.0 V to 3.6 V supply (typical 3.3 V), reflecting the L-suffix low-voltage variant of the classic XC3000 architecture.

An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of an array of configurable logic blocks, interconnect routing, and programmable I/O cells that can be electrically configured by the end user to implement arbitrary digital logic. FPGAs occupy the middle ground between fixed-function ASICs and software-programmable microcontrollers, offering parallel hardware execution, deterministic timing, and on-the-fly reconfigurability. The XC3000L family sits at the foundation of SRAM-based FPGA technology, with logical hierarchy: CLB -> logic cell array -> FPGA -> programmable logic device (PLD) -> digital integrated circuit.

Key features of the XC3090L-125PC84C include 320 CLBs delivering roughly 5,000 usable gates, 928 edge-triggered flip-flops for pipelined or state-machine designs, a maximum toggle rate of 125 MHz, and 84 PLCC pins providing programmable I/O plus dedicated configuration, clock and JTAG interfaces. The device supports JTAG (IEEE 1149.1) boundary-scan for board-level test, in-system reprogrammability through the standard Xilinx XC3000 configuration bitstream, and a power-down mode that significantly reduces quiescent current for battery-friendly applications.

Architecturally, the XC3090L implements the classic Xilinx XC3000 CLB with a 5-input lookup table feeding two flip-flops, a programmable interconnect matrix of single-length and double-length lines, and tri-state buffers that allow efficient implementation of muxes, busses, and tri-state I/O. The 125 MHz speed grade places it in the highest tier of the XC3090L family, enabling high-performance glue logic, custom state machines, and DSP-style bit-level pipelines on a single chip.

Typical applications include legacy telecom interface glue logic, industrial control and instrumentation front ends, custom peripheral controllers for microprocessor systems, prototyping vehicles for ASIC verification, and reconfigurable test fixtures. Designers building long-life industrial equipment, military refresh programs, or replacement boards for existing XC3000-based systems remain the primary users of this classic part. Designers using the XC3090L-125PC84C should preserve the legacy 3.3 V supply rail, follow Xilinx XC3000 configuration mode recommendations (SelectMAP/serial master or slave), and respect the PLCC pin-out when laying out new PCBs or repairing legacy boards.

This page combines distributor pricing, verified cross-reference data, and design notes that are not collected in the original Xilinx datasheet.

Alternatives de remplacement direct pour XC3090L-125PC84C — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec XC3090L-125PC84C (même facteur de forme et même empreinte) — différant par Package, Mounting Type, Family, Process Technology, Configuration Method.

EPM9560RC208-20

Intel

Package: 208-pin RQFP (28x28 mm)