Intel

EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel

Référence : EPM9560RC208-20 ✗ Fin de vie

En stock Expédié sous 1 à 3 jours ouvrés

5.0 V Vdss 5.0 V TTL/CMOS compatible Rds(on) 208-pin RQFP (28x28 mm) Package 100 MHz Speed

Contact pour connaître le prix

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$0	$0,00
10	$0	$0,00
100	$0	$0,00
500	$0	$0,00
1 000	$0	$0,00

ℹ️ Tous les prix sont en USD

Voir la fiche technique (PDF) Voir les alternatives

Quantité

EPM9560RC208-20 Présentation

The Intel (Altera) EPM9560RC208-20 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (Power Quad Flat Pack) surface-mount package. It operates from a 5.0 V supply with in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic array blocks and macrocells into a single non-volatile device, allowing designers to implement custom digital logic without fabricating an ASIC. Within the programmable logic hierarchy, a CPLD sits between simple PLDs and FPGAs: it offers lower density than an FPGA but provides deterministic, non-volatile, single-chip operation with predictable timing. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using CMOS EEPROM technology.

Key features of the EPM9560RC208-20 include 560 macrocells organized into 35 logic array blocks, 153 user I/O pins, 12,000 gates of logic capacity, and a 20 ns pin-to-pin delay that supports system clock rates up to 100 MHz. The EEPROM-based configuration is retained without external configuration memory, eliminating the boot-time configuration step required by SRAM-based FPGAs.

The MAX 9000 architecture uses a continuous interconnect scheme that delivers uniform, predictable propagation delays independent of routing, which simplifies static timing analysis. The 5.0 V core and I/O operation provides direct TTL/CMOS compatibility for legacy 5 V systems, and the built-in JTAG boundary-scan interface supports both in-system programming and board-level test.

Typical applications include glue logic for legacy 5 V microprocessor buses, PCI and ISA interface bridging, industrial control state machines, and replacement of discrete 74-series logic in existing designs. The 208-pin RQFP package is form, fit, and functionally equivalent to the discontinued 208-pin CQFP version, per Altera's product discontinuance notice.

When designing with this device, note that the MAX 9000 family is a mature, legacy product line; verify current availability and consider migration to a modern CPLD or small FPGA for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

Alternatives de remplacement direct pour EPM9560RC208-20 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9560RC208-20 (même facteur de forme et même empreinte) — différant par Package, Propagation Delay (tPD), Usable Gates, Pin-to-Pin Delay (tPD), Speed Grade.

EPM9480RC208-15

Intel

Package: RQFP-208

Propagation Delay (tPD): 15 ns

Usable Gates: 10,000 gates