2EDL8124GXUMA1 vs 2ED21064S06JXUMA1 Perbandingan
Perbandingan bersamaan detil 2EDL8124GXUMA1 dari Infineon dan 2ED21064S06JXUMA1 dari Infineon. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Infineon
2EDL8124GXUMA1 - 120V Boot 4A Junction-isolated Gate Driver | Infineon
2EDL8124GXUMA1 ✓ AktifPerbandingan Spesifikasi
| Parameter Umum | 2EDL8124GXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Merek | Infineon | Infineon |
| Kategori | Power MOSFET Drivers | Power MOSFET Drivers |
| Status Lingkungan Hidup | Aktif | Aktif |
| Driver Configuration | Half-bridge (high-side + low-side) | — |
| Input Type | Non-inverting, TTL-compatible with hysteresis | — |
| Number of Drivers | 2 | — |
| Peak Source Current | 3 A | — |
| Peak Sink Current | 4 A | — |
| Bootstrap Supply (VBS) Maximum | 120 V | — |
| VCC Supply Range | [DATA_NEEDED: VCC min/max typical range] | — |
| Isolation Type | Junction isolation (JI) | — |
| Bootstrap Diode | Integrated | Integrated |
| Propagation Delay (typical) | < 50 ns | 100 ns |
| Delay Matching Between Channels | [DATA_NEEDED: delay matching spec in ns] | — |
| UVLO | Present on VCC and VBS | — |
| Rentang Suhu Kerja | [DATA_NEEDED: operating temperature range in C] | — |
| Paket | PG-VDSON-8-4 (4 mm x 4 mm) with exposed pad | PG-DSO-14 (14-pin SOIC) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Level MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Status RoHS | Compliant | ROHS3 Compliant |
| Lead-Free | Yes | — |
| Fungsi | — | High-Side and Low-Side Gate Driver |
| Configuration | — | Half-Bridge (2 outputs, non-inverting) |
| Topologi | — | High-Side, Low-Side with integrated bootstrap diode |
| Maximum Offset / Boot Voltage | — | 650 V |
| Supply Voltage (VCC) | — | 10 V to 20 V |
| Source Current (typical) | — | 0.29 A |
| Sink Current (typical) | — | 0.7 A |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Suhu Kerja | — | -40C to +125C |
| Negative Gate Drive Robustness | — | -0.7 V |