EP3SE260F1517I4N vs EP3SE260F1517I4LN Perbandingan
Perbandingan bersamaan detil EP3SE260F1517I4N dari Intel dan EP3SE260F1517I4LN dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EP3SE260F1517I4N - Stratix III E FPGA, 255K LE, 1517-BGA | Intel
EP3SE260F1517I4N ⚠ Waktu Beli TerakhirIntel
EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel
EP3SE260F1517I4LN ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP3SE260F1517I4N | EP3SE260F1517I4LN |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Waktu Pembelian Terakhir |
| Series | Stratix III E | — |
| Logic Elements | 255,000 | 255,000 |
| Embedded Memory Bits | 16,672,768 bits | 16,672,768 bits (~2,044 KBytes) |
| Embedded Memory (M9K/M144K blocks) | [DATA_NEEDED: total Kbits and block count] | — |
| User I/O Pins | 976 | — |
| Transceivers | [DATA_NEEDED: number of full-duplex channels] | Stratix III E family supports up to 24 transceivers up to 8.5 Gbps |
| Transceiver Data Rate | 600 Mbps to 6.375 Gbps | — |
| DSP Blocks | [DATA_NEEDED: number of 18x18 multipliers] | — |
| PLLs | [DATA_NEEDED: total PLL count] | — |
| Core Voltage | 1.1 V | — |
| Process Technology | TSMC 65 nm | 40 nm CMOS |
| Paket | 1517-BBGA, FCBGA | 1517-ball FCBGA (40 mm x 40 mm, 1.0 mm pitch) |
| Package Body Size | [DATA_NEEDED: mm x mm] | — |
| Suhu Kerja | -40 °C to +100 °C (Industrial) | -40C to +100C (case, industrial) |
| Operating Temperature Grade | Industrial (I4) | — |
| Tipe Mounting | Surface Mount (BGA) | — |
| Lead-Free / RoHS | [DATA_NEEDED: explicit RoHS statement] | Yes (N suffix) |
| Level MSL | [DATA_NEEDED: MSL classification] | — |
| Logic Array Blocks (LABs) | — | 10,200 |
| User I/O Count | — | 976 |
| Family | — | Stratix III E (Enhanced) |
| Speed Grade | — | I4 (industrial, 4th tier) |
| Power Option | — | L (low-power) |
| DSP Blocks (18x18 multipliers) | — | Up to 384 (family-level, device-specific count not in provided data) |
| Partial Reconfiguration | — | Supported |
| Memory Interface Support | — | DDR3, DDR2, QDR II+ (hardened PHY) |
| Configuration Scheme | — | Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), JTAG |