EPC2LC20NA vs EPC2LC20V Perbandingan
Perbandingan bersamaan detil EPC2LC20NA dari Altera dan EPC2LC20V dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2LC20NA | EPC2LC20V |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | NRND |
| Manufacturer | Altera Corporation (Intel Programmable Solutions Group) | — |
| Tipe Memori | Configuration PROM (Flash-based, ISP) | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | 3.0 V to 3.6 V (3.3 V typ.) |
| Antarmuka | Serial (passive-serial) data output to FPGA | — |
| Programmability | In-system programmable via IEEE 1532 JTAG | — |
| Paket | 20-pin PLCC (9x9 mm) | PLCC-20 (JEDEC MO-047) |
| Tipe Mounting | Surface Mount (PLCC socket compatible) | — |
| Suhu Kerja | -40C to +85C (industrial grade) | -40C to +85C (industrial) |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury | — |
| JTAG Compliance | IEEE Std 1149.1 / IEEE 1532 | — |
| Configuration Mode | Passive Serial (PS) | — |
| Status RoHS | [DATA_NEEDED: rohs status] | — |
| Daisy-Chain Support | Yes | — |
| Recommended Companion FPGA | Altera Cyclone, FLEX 10K, APEX 20K series | — |
| Product Type | — | Flash Configuration Device (FPGA configuration PROM) |
| Ukuran Memori | — | 1.6 Mb (1,678,336 bits) |
| Configuration Interface | — | Serial (Passive Serial) or 8-bit parallel |
| Maximum Configuration Clock | — | 10 MHz |
| Program/Erase Cycles | — | 100,000 cycles minimum |
| Data Retention | — | 20 years minimum |
| JTAG Support | — | IEEE 1149.1 Boundary Scan, in-system programmable |
| Storage Temperature | — | -65C to +150C |
| Lead-Free / RoHS | — | Lead-free (V suffix), RoHS compliant |
| Compatible FPGAs | — | Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000 |
| On-chip Oscillator | — | Yes (generates DCLK) |
| Configuration Time (typical) | — | Depends on FPGA bitstream length and clock mode |
| Level MSL | — | [DATA_NEEDED: MSL level] |