EPC2LC20NA vs EPC2LC20V Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20NA sa pamamagitan ng Altera at EPC2LC20V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPC2LC20NA EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPC2LC20NA EPC2LC20V
Brand Altera Intel
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Manufacturer Altera Corporation (Intel Programmable Solutions Group) —
Uri ng Memory Configuration PROM (Flash-based, ISP) —
Memory Density 1.6 Mbit —
Operating Voltage (VCC) 3.3 V 3.0 V to 3.6 V (3.3 V typ.)
Interface Serial (passive-serial) data output to FPGA —
Programmability In-system programmable via IEEE 1532 JTAG —
Packhaging 20-pin PLCC (9x9 mm) PLCC-20 (JEDEC MO-047)
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) —
Temperature na Operasyon -40C to +85C (industrial grade) -40C to +85C (industrial)
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury —
JTAG Compliance IEEE Std 1149.1 / IEEE 1532 —
Configuration Mode Passive Serial (PS) —
Tindminan RoHS [DATA_NEEDED: rohs status] —
Daisy-Chain Support Yes —
Recommended Companion FPGA Altera Cyclone, FLEX 10K, APEX 20K series —
Product Type — Flash Configuration Device (FPGA configuration PROM)
Laki ng Memory — 1.6 Mb (1,678,336 bits)
Configuration Interface — Serial (Passive Serial) or 8-bit parallel
Maximum Configuration Clock — 10 MHz
Program/Erase Cycles — 100,000 cycles minimum
Data Retention — 20 years minimum
JTAG Support — IEEE 1149.1 Boundary Scan, in-system programmable
Storage Temperature — -65C to +150C
Lead-Free / RoHS — Lead-free (V suffix), RoHS compliant
Compatible FPGAs — Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000
On-chip Oscillator — Yes (generates DCLK)
Configuration Time (typical) — Depends on FPGA bitstream length and clock mode
Level ng MSL — [DATA_NEEDED: MSL level]

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