EPC2LC20NA vs EPC2LC20V Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC2LC20NA disebabkan oleh Altera dan EPC2LC20V disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPC2LC20NA EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPC2LC20NA EPC2LC20V
Merek Altera Intel
Kategori Memory ICs FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli NRND
Manufacturer Altera Corporation (Intel Programmable Solutions Group) —
Jenis Ingatan Configuration PROM (Flash-based, ISP) —
Memory Density 1.6 Mbit —
Operating Voltage (VCC) 3.3 V 3.0 V to 3.6 V (3.3 V typ.)
Antaramuka Serial (passive-serial) data output to FPGA —
Programmability In-system programmable via IEEE 1532 JTAG —
Kemasan 20-pin PLCC (9x9 mm) PLCC-20 (JEDEC MO-047)
Jenis Pemasangan Surface Mount (PLCC socket compatible) —
Suhu Operasi -40C to +85C (industrial grade) -40C to +85C (industrial)
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury —
JTAG Compliance IEEE Std 1149.1 / IEEE 1532 —
Configuration Mode Passive Serial (PS) —
Status RoHS [DATA_NEEDED: rohs status] —
Daisy-Chain Support Yes —
Recommended Companion FPGA Altera Cyclone, FLEX 10K, APEX 20K series —
Product Type — Flash Configuration Device (FPGA configuration PROM)
Saiz Ingatan — 1.6 Mb (1,678,336 bits)
Configuration Interface — Serial (Passive Serial) or 8-bit parallel
Maximum Configuration Clock — 10 MHz
Program/Erase Cycles — 100,000 cycles minimum
Data Retention — 20 years minimum
JTAG Support — IEEE 1149.1 Boundary Scan, in-system programmable
Storage Temperature — -65C to +150C
Lead-Free / RoHS — Lead-free (V suffix), RoHS compliant
Compatible FPGAs — Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000
On-chip Oscillator — Yes (generates DCLK)
Configuration Time (typical) — Depends on FPGA bitstream length and clock mode
Aras MSL — [DATA_NEEDED: MSL level]

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga