EPM5192LC-25 vs EPM5192LC-2N Perbandingan

Perbandingan bersamaan detil EPM5192LC-25 dari Altera dan EPM5192LC-2N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM5192LC-25 EPM5192LC-2N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) 192 macrocells (PAL/GAL-style AND-OR array)
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) -2 (tPD approximately 25 ns)
Paket JLCC-84 (ceramic J-lead chip carrier) —
Tipe Mounting Surface Mount Surface Mount (LC package)
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) Altera programming hardware (MAX+PLUS II / ByteBlaster compatible)
Suhu Kerja 0C to +70C (commercial) Commercial (0C to +70C) - inferred from speed-grade -2 designation
Tegangan Pemuat 5 V (typical, MAX 5000) 5 V (typical)
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) —
Manufacturer Altera Corporation (now Intel PSG) —
Status RoHS Unknown (legacy ceramic package typically non-RoHS) Compliant (per -N lead-free suffix)
Flip-Flops — 192
Package Type — LC (ceramic J-leaded, windowed UV-erasable package family)
Propagation Delay (typical) — 25 ns
Programmability — UV-erasable EPROM cell
Lead-Free — Yes (per -N suffix)
Architecture — Programmable Logic Array (PLA) with global PIA

Spek dan Sumber

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