EPM5192LC-25 vs EPM5192LC-2N 比較
詳細並排比較 EPM5192LC-25 由 Altera 與 EPM5192LC-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-25 | EPM5192LC-2N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | 192 macrocells (PAL/GAL-style AND-OR array) |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | -2 (tPD approximately 25 ns) |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) | — |
| 安裝類型 | Surface Mount | Surface Mount (LC package) |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| 供應電壓 | 5 V (typical, MAX 5000) | 5 V (typical) |
| I/O Standard | TTL-compatible | — |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) | Compliant (per -N lead-free suffix) |
| Flip-Flops | — | 192 |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |