EPM5192LI-1 vs EPM5192JI-2 Perbandingan
Perbandingan bersamaan detil EPM5192LI-1 dari Altera dan EPM5192JI-2 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5192LI-1 | EPM5192JI-2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 3,750 | 5000 |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| Tegangan Pemuat | 5 V | 5 V (typical) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | — |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Speed Grade | -1 | -2 |
| Suhu Kerja | [DATA_NEEDED: industrial vs military range] | 0C to +70C (commercial) |
| Jumlah Pin | [DATA_NEEDED: pin count of LI package] | — |
| Tipe Mounting | Surface Mount (JLCC with J-leads) | Surface Mount |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status of ceramic LI variant] | Non-compliant (ceramic JLCC, contains lead) |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | Sum-of-products with Programmable Interconnect Array (PIA) |
| Dedicated Inputs | — | 12 |
| Flip-Flops | — | 192 |
| Paket | — | JLCC-68 (J-Lead Ceramic) |
| Programming Technology | — | UV-Erasable EPROM |
| Status Lingkungan Hidup | — | Obsolete (legacy Altera MAX 5000 family) |