EPM5192LI-1 vs EPM5192JI-2 比較
詳細並排比較 EPM5192LI-1 由 Altera 與 EPM5192JI-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LI-1 | EPM5192JI-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 3,750 | 5000 |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| 供應電壓 | 5 V | 5 V (typical) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | — |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Speed Grade | -1 | -2 |
| 工作溫度 | [DATA_NEEDED: industrial vs military range] | 0C to +70C (commercial) |
| 腳位數 | [DATA_NEEDED: pin count of LI package] | — |
| 安裝類型 | Surface Mount (JLCC with J-leads) | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of ceramic LI variant] | Non-compliant (ceramic JLCC, contains lead) |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | Sum-of-products with Programmable Interconnect Array (PIA) |
| Dedicated Inputs | — | 12 |
| Flip-Flops | — | 192 |
| 封裝 | — | JLCC-68 (J-Lead Ceramic) |
| Programming Technology | — | UV-Erasable EPROM |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 5000 family) |