EPM5192LI-1 vs EPM5192JI-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI-1 sa pamamagitan ng Altera at EPM5192JI-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LI-1 | EPM5192JI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 3,750 | 5000 |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| Volte ng Pagbibigay | 5 V | 5 V (typical) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | — |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Speed Grade | -1 | -2 |
| Temperature na Operasyon | [DATA_NEEDED: industrial vs military range] | 0C to +70C (commercial) |
| Bilang ng Pin | [DATA_NEEDED: pin count of LI package] | — |
| Uri ng Pagpapasok | Surface Mount (JLCC with J-leads) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status of ceramic LI variant] | Non-compliant (ceramic JLCC, contains lead) |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | Sum-of-products with Programmable Interconnect Array (PIA) |
| Dedicated Inputs | — | 12 |
| Flip-Flops | — | 192 |
| Packhaging | — | JLCC-68 (J-Lead Ceramic) |
| Programming Technology | — | UV-Erasable EPROM |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 5000 family) |