10AS066H1F34I1HG - Arria 10 SX SoC FPGA, 660K LE | Intel
部品番号: 10AS066H1F34I1HG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4310 | $431,000.00 |
| 500 | $3990 | $1,995,000.00 |
| 1,000 | $3720 | $3,720,000.00 |
10AS066H1F34I1HG 概要
An SoC FPGA is an integrated circuit that combines a programmable logic fabric (the FPGA side) with one or more hard processor cores (the HPS side) on the same die. Compared with a discrete FPGA + external MCU/MPU architecture, this integration eliminates inter-chip PCB traces between processor and fabric, reducing latency, board area, bill-of-materials cost, and power while enabling tight co-design of hardware accelerators with software. The Arria 10 SX family sits in Intel's mid-range, transceiver-rich segment, positioned between lower-cost Cyclone/MAX families and the high-end Stratix 10 family.
Key features include approximately 660K logic elements, embedded hardened memory and DSP blocks, high-speed transceivers, and a 32-bit DDR3/DDR4 capable HPS memory controller. The 1152-ball FCBGA package exposes all transceiver, HPS, and general-purpose I/O signals and is suitable for high-channel-count designs. Industrial temperature grade (I) is indicated by the part number suffix. According to the Altera/Intel Arria 10 device overview, the SX variant pairs the HPS with the FPGA fabric optimized for DSP and transceiver-heavy workloads.
Typical applications include high-performance digital signal processing for wireless baseband, radar and electronic warfare, professional video broadcast and image processing, industrial machine vision and motor control, and high-throughput data acquisition. The integrated ARM Cortex-A9 cores allow Linux/RTOS deployment alongside custom hardware accelerators in the FPGA fabric, removing the need for an external application processor.
When designing with this device, plan power-rail sequencing between the HPS and FPGA domains and provide adequate thermal relief: the FCBGA package requires a heatsink or thermal interface material for sustained high-performance operation. Quartus Prime software (Standard or Pro edition, depending on device support) is required for synthesis, place-and-route, and HPS configuration.
ドロップイン代替品: 10AS066H1F34I1HG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AS066H1F34I1HG （同一形状・フットプリント） — 相違点: Package, Logic Elements, Operating Temperature, Speed Grade, Temperature Grade.
クイック比較ツール — 並列比較する代替部品を選択:
10AS066H1F34E1HG
✅ ドロップイン✓ 在庫あり
$3900 / 個
データシートを見る →10AS066H1F34I1SG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
10AS057H1F34I1HG
✅ ドロップイン✓ 在庫あり
$3500 / 個
データシートを見る →10AS048H1F34I1HG
✅ ドロップイン✓ 在庫あり
$2650 / 個
データシートを見る →10AS032H1F34I1HG
✅ ドロップイン✓ 在庫あり
$2077.26 / 個
データシートを見る →10AS066H1F34I1HG 最大定格＆電気的特性
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660000 (approx.) |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Core Frequency | 1.5 GHz (max) |
| Process Technology | 20 nm |
| パッケージ | 1152-ball FC-FBGA (35 x 35 mm) |
| Operating Temperature Grade | Industrial (-40C to +100C, suffix I) |
| RoHS ステータス | Compliant |
| 実装タイプ | Surface Mount (BGA) |
| Maximum Seated Height | 3.35 mm |
| Terminal Form | BALL |
| Number of Terminals | 1152 |
| Package Code | BGA |
| Package Shape | SQUARE |
| Lead Free | Yes (per Altera product page) |
| Configuration Memory | SRAM-based (volatile) |
10AS066H1F34I1HG square ピン配置ガイド
10AS066H1F34I1HG (square パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 10AS066H1F34I1HG.
詳細は データシート をご参照ください。
主な用途
10AS066H1F34I1HG の用途: 7 件s: Wireless Baseband Processing, Radar and Electronic Warfare, Professional Video Broadcast and Image Processing, Industrial Machine Vision and Motor Control, High-Throughput Data Acquisition, 5G Fronthaul and PHY Acceleration, Medical Imaging Equipment.
Wireless Baseband Processing
The 10AS066H1F34I1HG suits wireless baseband designs where the 660K logic elements and hardened DSP blocks implement high-throughput channel cards, while the dual 1.5 GHz ARM Cortex-A9 cores run the MAC scheduler and protocol stack. Its industrial temperature grade supports outdoor small-cell and pico-cell deployments. Compared with a discrete FPGA + MCU design, the integrated HPS removes inter-chip latency and board area.
おすすめ
Radar and Electronic Warfare
In radar and EW systems, the 10AS066H1F34I1HG's hardened floating-point DSP blocks and high-speed transceivers process wideband I/Q streams directly, while the HPS runs tracker and classification algorithms. The 1152-ball F34 package exposes the full transceiver count needed for multi-channel phased-array receivers. The industrial temperature grade enables platform deployments in unconditioned enclosures.
おすすめ
Professional Video Broadcast and Image Processing
Broadcast video routers, multi-viewers, and 4K/8K image-processing pipelines benefit from the 10AS066H1F34I1HG's combination of 660K logic elements, on-chip memory, and the integrated HPS for control-plane networking. The SoC runs Linux for IP-based control while the FPGA fabric handles pixel-rate processing. Industrial temperature grade supports studio and outdoor-broadcast equipment racks.
おすすめ
Industrial Machine Vision and Motor Control
Factory automation cameras and high-precision motor drives use the 10AS066H1F34I1HG to run multi-axis control loops and image-pipeline preprocessing simultaneously. The HPS executes motion-control software under a real-time OS while the FPGA fabric handles encoder decoding and image preprocessing. The industrial temperature grade and -40C to +100C range suit factory-floor conditions.
おすすめ
High-Throughput Data Acquisition
Test and measurement instruments and high-channel-count DAQ systems pair the 10AS066H1F34I1HG's transceivers and parallel I/O with the HPS for data forwarding over 10 Gigabit Ethernet or PCIe. The SoC enables real-time DSP in fabric and Linux-side storage simultaneously, eliminating a separate processor card. Industrial temperature grade supports lab and field-instrument deployments.
おすすめ
5G Fronthaul and PHY Acceleration
The 10AS066H1F34I1HG accelerates 5G PHY-layer functions such as LDPC decoding, FFT/iFFT, and digital pre-distortion in the FPGA fabric, while the dual 1.5 GHz ARM Cortex-A9 HPS handles fronthaul networking under Linux. Its hardened DSP and transceiver count suit mid-band radio units. Industrial temperature grade supports outdoor radio-unit enclosures.
おすすめ
Medical Imaging Equipment
Ultrasound and CT imaging systems use the 10AS066H1F34I1HG to perform beamforming and image reconstruction in the FPGA fabric, while the HPS runs the user interface and DICOM networking stack. The SoC reduces board count compared with discrete designs and the industrial temperature grade supports hospital and mobile-clinic environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AS066H1F34I1HG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AS066H1F34E1HG | 10AS057H1F34I1HG | 10AS048H1F34I1HG | 10AS032H1F34I1HG |
|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (F34, 35x35 mm) | 1152-ball FC-FBGA (F34, 35x35 mm) | 1152-ball FC-FBGA (F34, 35x35 mm) | 1152-ball FC-FBGA (F34, 35x35 mm) | 1152-ball FC-FBGA (F34, 35x35 mm) |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 660000 | 660000 | 570000 | 480000 | 320000 |
| Hard Processor System | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz | Dual ARM Cortex-A9, 1.5 GHz |
| Temperature Grade | Industrial (-40C to +100C) | Extended | Industrial | Industrial | Industrial |
| Speed Grade | -1 | -1 | -1 | -1 | -1 |
| Process Node | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Pin/Package Compatibility | Reference | Drop-in (same F34 BGA) | Drop-in (same F34 BGA, lower LE) | Drop-in (same F34 BGA, lower LE) | Drop-in (same F34 BGA, lower LE) |
主な差別化要因
- Integrated ARM Cortex-A9 HPS at 1.5 GHz alongside 660K LE fabric （vs 10AS057H1F34I1HG (570K LE))
- Industrial temperature grade on a 660K-LE SX die （vs 10AS066H1F34E1HG (extended temperature))
- Pin-compatible density scaling within the F34 footprint （vs 10AS032H1F34I1HG (320K LE))
- 20 nm process with hardened floating-point DSP （vs 10AS048H1F34I1HG (480K LE))
設計ノート
Estimated: The 1152-ball FC-FBGA 35 x 35 mm Arria 10 SX package dissipates 15-30 W under sustained workload depending on toggle rate and transceiver utilisation. With a typical theta_JA of around 8 C/W, junction temperature can rise 120-240 C above ambient without thermal relief. A heatsink with thermal interface material and adequate airflow is required for industrial-temperature operation. Confirm exact theta values against the latest Intel Arria 10 Device Datasheet.
Arria 10 SX SoCs require multiple power rails (core VCC, VCCPT, VCCAUX, VCCR, transceiver supplies, HPS supplies). Sequence rails according to the Intel Arria 10 Power Management User Guide to avoid latch-up. Use the Altera/Intel PowerPlay early power estimator to size regulators before final schematic. Estimated: budget 25 W of regulator capacity for a typical 660K-LE SX design with 4 transceiver channels at full utilisation.
The 1152-ball F34 BGA has a 1.0 mm ball pitch. Use at least 8 PCB layers with HDI micro-via stack-ups (any-layer via preferred). Match trace lengths within each transceiver bank to within the limits in the Intel Arria 10 Transceiver User Guide; length matching within 150 mils is typical for 10 Gbps channels. Decouple every VCC pin individually with 0402 or 0201 ceramic capacitors.
Do not omit the configuration device. Arria 10 SRAM-based FPGAs lose configuration on power-down and require a serial flash (EPCQ-L) plus the appropriate MSEL pin strapping for fast/standard/remote configuration. For HPS boot, populate the QSPI flash and SD card boot interface; ensure the boot mode pins are correctly strapped on reset.
Transceiver channels on Arria 10 SX require controlled-impedance 100-ohm differential routing with AC coupling capacitors at the device pins. Reference the Intel Arria 10 Transceiver User Guide for the recommended AC-coupling capacitor value, typically 100 nF for data rates up to 10 Gbps and 10 nF for 25 Gbps channels. Estimated: budget 4-8 transceiver channels per fabric-side interface card for typical mid-band radio units.
コンプライアンス情報
RoHS and lead-free per Altera/Intel product page. AEC-Q100 not applicable for SoC FPGA. Halogen-free status marked as unknown - not stated explicitly in retrieved distributor data.
