ADC10D020CIVS - Dual 10-Bit 20MSPS 150mW ADC | Texas Instruments
部品番号: ADC10D020CIVS ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.85 | $5,925.00 |
| 1,000 | $9.8 | $9,800.00 |
ADC10D020CIVS 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. The ADC10D020 belongs to the successive-approximation/pipeline hybrid converter family within the broader data converter hierarchy (data converter -> ADC -> high-speed ADC -> dual ADC). Dual-channel ADCs are widely used in communications, imaging, and instrumentation where simultaneous or interleaved sampling reduces system cost and board area versus two discrete converters.
Key features of the ADC10D020CIVS include a separate digital I/O supply (1.5 V to 3.6 V) for direct interfacing to low-voltage ASICs and FPGAs, an internal reference, and a two-step flash architecture that balances power and speed. The dual channels can be configured for simultaneous sampling, interleaved operation at up to 40 MSPS effective rate, or independent single-channel use. Power-down modes reduce consumption to under 1 mW for portable or duty-cycled applications.
The 48-pin TQFP (7x7) package provides a robust industrial-grade footprint with adequate thermal performance (theta-JA approximately 60 C/W typical) for fanless operation. The device uses a two-step pipeline architecture to achieve low latency, making it suitable for control-loop and real-time signal processing applications. Digital outputs are CMOS-compatible, and the analog inputs are differential, supporting both AC- and DC-coupled input signals.
Typical applications for the ADC10D020CIVS include video digitizers, communications IF/baseband receivers, portable test instruments, CCD/camera imaging front-ends, and ultrasound or medical imaging subsystems. Its dual-channel configuration is especially valuable where matched, simultaneous sampling of two signal paths is required - for example, I/Q demodulation in software-defined radio.
When designing with this ADC, ensure the analog input common-mode voltage and drive impedance are matched to the ADC's input structure to preserve spurious-free dynamic range (SFDR). Place the analog and digital ground planes with care, and decouple AVDD and DVDD separately. The separate DRVDD pin allows mixed-voltage system integration without level shifters.
ドロップイン代替品: ADC10D020CIVS — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC10D020CIVS （同一形状・フットプリント） — 相違点: Architecture, Input Type, Package, Reference, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ADC10D020CIVS/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC10D020CIVSX/NOPB
✅ ドロップイン✓ 在庫あり
$10.85 / 個
データシートを見る →ADC10D020CIVT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC10D020CIVS 最大定格＆電気的特性
| 分解能 | 10 bit |
| Number of Channels | 2 |
| Sampling Rate (Dual-Channel) | 20 MSPS |
| Sampling Rate (Single-Channel) | 30 MSPS |
| Architecture | Two-step (sub-ranging) flash |
| Analog Supply Voltage | 2.7 V to 3.6 V (3.0 V typical) |
| Digital I/O Supply Voltage (DRVDD) | 1.5 V to 3.6 V |
| Power Consumption (Typ) | 150 mW at 3.0 V, 20 MSPS |
| Power-Down Current | < 1 mA typical |
| Input Type | Differential analog inputs |
| Output Interface | Parallel CMOS (10-bit per channel) |
| 動作温度範囲 | -40C to +85C |
| パッケージ | 48-pin TQFP (7x7 mm, IVT suffix) |
| 実装タイプ | Surface Mount |
| MSLレベル | 2 (1 year floor life at <30C/60% RH) |
| RoHS ステータス | Compliant |
| Reference | Internal (external reference option) |
ADC10D020CIVS ピン構成
| ピン 1 | DRVDD — Digital output driver supply voltage |
| ピン 2 | DGND — Digital ground |
| ピン 3 | D0A — Channel A digital output bit 0 (LSB) |
| ピン 4 | D1A — Channel A digital output bit 1 |
| ピン 5 | D2A — Channel A digital output bit 2 |
| ピン 6 | D3A — Channel A digital output bit 3 |
| ピン 7 | D4A — Channel A digital output bit 4 |
| ピン 8 | D5A — Channel A digital output bit 5 |
| ピン 9 | D6A — Channel A digital output bit 6 |
| ピン 10 | D7A — Channel A digital output bit 7 |
| ピン 11 | D8A — Channel A digital output bit 8 |
| ピン 12 | D9A — Channel A digital output bit 9 (MSB) |
| ピン 13 | DGND — Digital ground |
| ピン 14 | DRVDD — Digital output driver supply voltage |
| ピン 15 | PD — Power-down input (active high) |
| ピン 16 | MODE — Mode select / interleaved configuration |
| ピン 17 | CAL — Calibration input |
| ピン 18 | CLK — Conversion clock input |
| ピン 19 | DRVDD — Digital output driver supply voltage |
| ピン 20 | D9B — Channel B digital output bit 9 (MSB) |
| ピン 21 | D8B — Channel B digital output bit 8 |
| ピン 22 | D7B — Channel B digital output bit 7 |
| ピン 23 | D6B — Channel B digital output bit 6 |
| ピン 24 | D5B — Channel B digital output bit 5 |
| ピン 25 | D4B — Channel B digital output bit 4 |
| ピン 26 | D3B — Channel B digital output bit 3 |
| ピン 27 | D2B — Channel B digital output bit 2 |
| ピン 28 | D1B — Channel B digital output bit 1 |
| ピン 29 | D0B — Channel B digital output bit 0 (LSB) |
| ピン 30 | DGND — Digital ground |
| ピン 31 | DRVDD — Digital output driver supply voltage |
| ピン 32 | VREF — Reference voltage bypass / external reference input |
| ピン 33 | AGND — Analog ground |
| ピン 34 | AVDD — Analog supply voltage (3.0 V typical) |
| ピン 35 | INA+ — Channel A positive differential analog input |
| ピン 36 | INA- — Channel A negative differential analog input |
| ピン 37 | AGND — Analog ground |
| ピン 38 | AVDD — Analog supply voltage (3.0 V typical) |
| ピン 39 | INB+ — Channel B positive differential analog input |
| ピン 40 | INB- — Channel B negative differential analog input |
| ピン 41 | AGND — Analog ground |
| ピン 42 | AVDD — Analog supply voltage (3.0 V typical) |
| ピン 43 | REFT — Reference top (decoupling) |
| ピン 44 | REFB — Reference bottom (decoupling) |
| ピン 45 | AGND — Analog ground |
| ピン 46 | AVDD — Analog supply voltage (3.0 V typical) |
| ピン 47 | NC — Not connected (per datasheet) |
| ピン 48 | NC — Not connected (per datasheet) |
主な用途
ADC10D020CIVS の用途: 6 件s: Video Digitizer / Broadcast Imaging, Communications IF / Baseband Receiver, Portable Test & Measurement Instrument, CCD / CMOS Camera Imaging Front-End, Medical Ultrasound / Diagnostic Imaging, Industrial Process Control / Data Acquisition.
Video Digitizer / Broadcast Imaging
The ADC10D020CIVS is well suited to broadcast video digitizer boards where two 10-bit channels simultaneously sample luminance (Y) and chrominance (C) or composite SD/HD signals at rates up to 20 MSPS per channel. Its 150 mW typical power budget and 3.0 V analog supply keep thermal load manageable in fanless 1U rack-mount frames, while the separate DRVDD pin (1.5-3.6 V) drives the FPGA video pipeline directly without level shifters. The 10-bit resolution is sufficient for 8-bit video workflows with headroom for color-space conversion and deinterlacing, and the dual-channel architecture halves board area compared to dual-ADC designs.
おすすめ
Communications IF / Baseband Receiver
In software-defined radio and IF-sampling receivers, the ADC10D020CIVS dual channels can simultaneously sample I and Q baseband signals at 20 MSPS per channel, preserving the amplitude and phase balance needed for demodulation. The 10-bit dynamic range suits narrowband digital communications, and the configurable single-channel mode boosts throughput to 30 MSPS for direct IF sampling up to ~75 MHz. Combined with its low 150 mW consumption and small 48-pin TQFP, the part is attractive for portable test equipment, tactical radios, and small-cell base-station monitoring where board area and power are constrained.
おすすめ
Portable Test & Measurement Instrument
Handheld oscilloscopes, data loggers, and spectrum-analyzer front-ends use the ADC10D020CIVS to digitize two channels of analog input at 20 MSPS while drawing only 150 mW from a 3.0 V rail - critical for battery-powered field instruments. The integrated dual channels eliminate the cost and matching issues of two single-channel ADCs, and the 1.5-3.6 V digital I/O supply lets the ADC interface directly to modern low-voltage FPGAs in compact form factors. The power-down mode (less than 1 mW) supports duty-cycled acquisition for extended battery life in field-deployed monitoring systems.
おすすめ
CCD / CMOS Camera Imaging Front-End
The ADC10D020CIVS dual-channel architecture supports dual-tap CCD or CMOS image sensors, simultaneously sampling the odd and even pixel outputs at 20 MSPS per channel to reconstruct the full-resolution image stream. The 10-bit resolution and 20 MSPS rate are well matched to standard VGA/XGA industrial cameras operating at 30-60 fps, and the separate digital I/O supply simplifies interface to image-processing ASICs. The 48-pin TQFP package is small enough for compact camera modules used in machine vision, barcode scanning, and surveillance systems.
おすすめ
Medical Ultrasound / Diagnostic Imaging
Ultrasound beamformers require matched, simultaneous sampling of multiple receive channels; the ADC10D020CIVS dual-channel integration simplifies multi-channel receiver design by halving the ADC count per board. The 10-bit resolution and 20 MSPS rate suit portable point-of-care ultrasound carts operating in the 2-10 MHz band, and the low 150 mW power budget keeps per-channel thermal load low enough for high-channel-count arrays. The industrial -40C to +85C temperature range also supports mobile clinical environments where ambient conditions are uncontrolled.
おすすめ
Industrial Process Control / Data Acquisition
Multi-channel industrial DAQ modules use the ADC10D020CIVS to digitize pairs of sensor outputs (e.g., strain gauge plus temperature, or vibration plus current) with matched timing for accurate differential measurements. The 10-bit resolution suits process-control loops with 0.1% setpoint accuracy, and the 20 MSPS rate captures fast transients such as motor inrush or solenoid switching for diagnostic logging. The 48-pin TQFP package withstands industrial reflow profiles, and the industrial -40C to +85C temperature range covers factory-floor deployment without active cooling.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC10D020CIVS — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC10D020CIVS/NOPB | ADC10D020CIVSX/NOPB | ADC10D020CIVT |
|---|---|---|---|---|
| Package | 48-pin TQFP (7x7 mm) | 48-pin TQFP (7x7 mm) - same | 48-pin TQFP (7x7 mm) - same | 48-pin TQFP (7x7 mm) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Sampling Rate (Dual) | 20 MSPS | 20 MSPS | 20 MSPS | 20 MSPS |
| Analog Supply | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| Power (typ) | 150 mW | 150 mW | 150 mW | 150 mW |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS / Lead-Free | Check variant | RoHS compliant, lead-free | RoHS compliant, lead-free | Standard (non-NOPB) |
主な差別化要因
- Lower per-channel power than dual-discrete ADC designs （vs Two single-channel 10-bit ADCs at equivalent sampling rate)
- Separate DRVDD rail for direct FPGA/ASIC interface （vs Older ADCs with single-supply output drivers)
- Configurable single-channel interleaved mode （vs Fixed dual-channel ADCs without interleaving)
設計ノート
Use a split ground plane with a single point connection between analog ground (AGND) and digital ground (DGND) directly under the ADC10D020CIVS. Decouple AVDD with 0.1 uF ceramic capacitors placed as close as possible to each AVDD pin, and add a 10 uF bulk capacitor near the supply entry point. Keep the analog input traces short and matched for the differential pair, and route digital outputs away from analog inputs to minimize digital coupling into the analog front-end.
Drive the analog inputs (INA+/INA-, INB+/INB-) with a low-impedance differential source to preserve the ADC's spurious-free dynamic range. The two-step architecture is sensitive to input common-mode voltage drift; use a common-mode reference network or transformer coupling. Clock the ADC with a low-jitter source - the SNR degrades rapidly with clock jitter above 1 ps RMS, especially at high input frequencies.
Separate AVDD and DRVDD supplies are recommended; even when both run from 3.3 V, use a ferrite bead or filter between them to prevent digital switching noise from coupling into the analog section. The power-down pin (PD) reduces consumption to less than 1 mW for duty-cycled operation, but allow 100 us of wake-up time before resuming conversions to let internal references settle.
Estimated: at typical 150 mW dissipation and a 48-pin TQFP (7x7) thermal resistance of approximately 60 C/W, the junction temperature rise above ambient is roughly 9C. This is well within safe operating limits for industrial deployments without active cooling, but in enclosed housings the system-level thermal envelope should still be checked.
Do not leave any AVDD or DRVDD pin unconnected - all supply pins must be powered for proper operation. Avoid using the ADC's reference voltage pin (VREF) as a general-purpose output; if external reference mode is selected, drive VREF with a low-noise source. The MODE pin configuration must match the actual channel usage; incorrect settings can cause channel swap or reduced dynamic range.
コンプライアンス情報
RoHS and lead-free compliance per Texas Instruments product information; choose /NOPB ordering suffix for explicit lead-free finish. Not AEC-Q100 qualified - this part targets industrial/commercial designs.
