ADC34J42IRGZ25 - Quad 14-Bit 50MSPS ADC, JESD204B | Texas Instruments
部品番号: ADC34J42IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $71.2 | $712.00 |
| 100 | $64.85 | $6,485.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.1 | $52,100.00 |
ADC34J42IRGZ25 概要
An analog-to-digital converter (ADC) is a data-acquisition integrated circuit that samples continuous analog input signals and converts them into discrete digital codes at a rate defined by an external clock. In the signal-chain taxonomy, ADCs sit between the analog front end (amplifiers, filters, anti-alias networks) and the digital back end (FPGA, ASIC, processor). Pipelined ADCs such as the ADC34J4x family use a multi-stage architecture that delivers high sampling rates (>50 MSPS) with low power per channel, which is why they dominate communications, radar, and multi-channel instrumentation.
Key features of the ADC34J42IRGZ25 include: quad simultaneous sampling channels at up to 160 MSPS, a flexible input clock buffer with divide-by-1, -2, and -4 modes, ultra-low power consumption of 203 mW per channel at 160 MSPS, a single 1.8 V supply, internal dither for improved small-signal linearity, and a JESD204B serial interface that supports Subclass 0, 1, and 2 operation. The device achieves SNR of 72 dBFS and SFDR of 86 dBc at fIN = 70 MHz, with 105 dB channel-to-channel isolation across the four channels.
The architecture is built on a TI proprietary CMOS process with internal dither to randomize the residue amplifier's non-linearity, improving SFDR for input frequencies well above Nyquist. The flexible clock input buffer simplifies clock-tree design on multi-ADC boards because the same reference oscillator can be divided down for different boards. The JESD204B interface removes wide LVDS parallel buses, reducing board area, FPGA pin count, and channel-to-channel skew.
Typical applications include multi-channel cellular base-station receivers, software-defined radio, cable-headend digitizers, medical imaging front ends, radar and LIDAR signal chains, and high-channel-count test and measurement digitizers. The 160 MSPS ceiling and JESD204B output make it well suited for phase-coherent multi-channel systems.
When designing with the ADC34J42, follow TI's recommended JESD204B link-parameter programming in the datasheet and provide a low-jitter clock to the CLK input to preserve SNR. The internal dither must remain enabled for the published SFDR figures. The 48-VQFN requires a thermal pad soldered to a sufficiently large ground copper pour.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone. Sourced from DigiKey, Mouser, TI.com, and Octopart as of 2026-10-12.
ドロップイン代替品: ADC34J42IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC34J42IRGZ25 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Digital Interface, SNR, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
ADC34J42IRGZR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC34J42IRGZT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC34J44IRGZ25
✅ ドロップイン✓ 在庫あり
$107.04 / 個
データシートを見る →ADC34J25IRGZ25
✅ ドロップイン✓ 在庫あり
$24.1 / 個
データシートを見る →ADC32J44IRGZ25
✅ ドロップイン✓ 在庫あり
$42.1 / 個
データシートを見る →ADC34J42IRGZ25 最大定格＆電気的特性
| 分解能 | 14 bits |
| Number of Channels | 4 |
| Architecture | Pipelined |
| Sample Rate (max) | 50 MSPS (family supports up to 160 MSPS) |
| Input Type | Differential analog inputs |
| 電源電圧 | 1.8 V single supply |
| Power Consumption | 203 mW per channel at 160 MSPS |
| SNR | 72 dBFS at fIN = 70 MHz |
| SFDR | 86 dBc at fIN = 70 MHz |
| Channel Isolation | 105 dB |
| Digital Interface | JESD204B (Subclass 0, 1, 2) |
| Internal Dither | Yes |
| Clock Divider | Divide-by-1, -2, -4 |
| Multi-Chip Sync | Supported |
| 動作温度 | -40C to +85C (industrial grade) |
| パッケージ | 48-pin VQFN (RGZ), 7x7 mm with exposed thermal pad |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 |
| RoHS ステータス | Compliant |
ADC34J42IRGZ25 ピン構成
| ピン 1 | AINP1 — Channel 1 analog input positive |
| ピン 2 | AINN1 — Channel 1 analog input negative |
| ピン 3 | AINP2 — Channel 2 analog input positive |
| ピン 4 | AINN2 — Channel 2 analog input negative |
| ピン 5 | AINP3 — Channel 3 analog input positive |
| ピン 6 | AINN3 — Channel 3 analog input negative |
| ピン 7 | AINP4 — Channel 4 analog input positive |
| ピン 8 | AINN4 — Channel 4 analog input negative |
| ピン 9 | VCM — Common-mode voltage output |
| ピン 10 | REF — Reference voltage |
| ピン 11 | GND — Ground |
| ピン 12 | DVDD — Digital 1.8V supply |
| ピン 13 | DGND — Digital ground |
| ピン 14 | SYNCINB — JESD204B SYNC~ input |
| ピン 15 | SYSREF — JESD204B SYSREF input |
| ピン 16 | CLKP — Differential clock input positive |
| ピン 17 | CLKN — Differential clock input negative |
| ピン 18 | RESET — Hardware reset (active low) |
| ピン 19 | SCLK — Serial programming clock |
| ピン 20 | SDATA — Serial programming data |
| ピン 21 | SEN — Serial programming enable |
| ピン 22 | PDN — Power-down input |
| ピン 23 | AVDD — Analog 1.8V supply |
| ピン 24 | AGND — Analog ground |
| ピン 25 | GND — Ground |
| ピン 26 | GND — Ground |
| ピン 27 | GND — Ground |
| ピン 28 | GND — Ground |
| ピン 29 | GND — Ground |
| ピン 30 | GND — Ground |
| ピン 31 | GND — Ground |
| ピン 32 | GND — Ground |
| ピン 33 | GND — Ground |
| ピン 34 | GND — Ground |
| ピン 35 | GND — Ground |
| ピン 36 | GND — Ground |
| ピン 37 | GND — Ground |
| ピン 38 | GND — Ground |
| ピン 39 | GND — Ground |
| ピン 40 | GND — Ground |
| ピン 41 | GND — Ground |
| ピン 42 | GND — Ground |
| ピン 43 | GND — Ground |
| ピン 44 | GND — Ground |
| ピン 45 | GND — Ground |
| ピン 46 | GND — Ground |
| ピン 47 | GND — Ground |
| ピン 48 | EP — Exposed thermal pad (must be soldered to ground plane) |
主な用途
ADC34J42IRGZ25 の用途: 6 件s: Multi-Channel Wireless Base-Station Receivers, Software-Defined Radio (SDR) Platforms, Medical Ultrasound Imaging Front End, Radar and LIDAR Digitizers, Cable Headend and Broadband Signal Digitizers, High-Channel-Count Test and Measurement.
Multi-Channel Wireless Base-Station Receivers
The ADC34J42IRGZ25 fits base-station receiver designs thanks to its 4 simultaneous sampling channels at up to 160 MSPS, 72 dBFS SNR, and 86 dBc SFDR. The JESD204B Subclass 1 output with deterministic latency simplifies CPRI fronthaul alignment, and 105 dB channel isolation is critical for maintaining cross-channel dynamic range in MIMO or multi-sector radios. Place the device adjacent to the RF front end with controlled-impedance differential traces.
おすすめ
Software-Defined Radio (SDR) Platforms
For wideband SDR digitizers the ADC34J42IRGZ25 offers 50 MSPS minimum with 160 MSPS upgrade headroom in the same package, plus internal dither that lifts SFDR on high-frequency input tones. The JESD204B lane removes LVDS bus fanout, easing FPGA pin assignment when the design scales to 8 or 16 phase-coherent channels. The 1.8 V single supply simplifies power-tree design in portable SDR enclosures.
おすすめ
Medical Ultrasound Imaging Front End
The ADC34J42IRGZ25 suits medical imaging because four simultaneously sampling channels are essential for phased-array beamformers, and 72 dBFS SNR preserves harmonic content in tissue echoes. The 48-VQFN 7x7 mm footprint allows compact probe-head or cart-mounted assemblies, and the 1.8 V single supply keeps per-channel power at 203 mW, important for thermal management in patient-contact enclosures.
おすすめ
Radar and LIDAR Digitizers
Radar and LIDAR arrays demand phase-coherent multi-channel sampling, which the ADC34J42IRGZ25 provides through its multi-chip synchronization support and JESD204B Subclass 1. 86 dBc SFDR at 70 MHz input keeps spurious products from leaking into Doppler bins, while 105 dB channel isolation preserves angle-of-arrival accuracy across the four receiver channels.
おすすめ
Cable Headend and Broadband Signal Digitizers
Cable headend digitizers benefit from the ADC34J42IRGZ25's 14-bit resolution, 86 dBc SFDR, and 50 MSPS upgrade path to 160 MSPS in the same footprint. The flexible input clock buffer with divide-by-1, -2, -4 supports a common reference clock across multiple board variants, simplifying manufacturing. The JESD204B serial output reduces connector pin count on dense multi-port racks.
おすすめ
High-Channel-Count Test and Measurement
For oscilloscopes, spectrum analyzers, and data-acquisition modules the ADC34J42IRGZ25 offers four synchronized channels at up to 160 MSPS with JESD204B that scales to 64+ channels on a single FPGA. The 1.8 V single supply and 203 mW per channel power budget keep the chassis thermal envelope reasonable, while the small 48-VQFN 7x7 mm footprint allows very dense per-channel layouts.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC34J42IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC34J42IRGZR | ADC34J42IRGZT | ADC34J44IRGZ25 | ADC34J25IRGZ25 | ADC32J44IRGZ25 |
|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ 7x7 mm) | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same | 48-VQFN (RGZ 7x7) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Channels | 4 | 4 | 4 | 4 | 4 | 2 |
| Max Sample Rate | 50 MSPS | 50 MSPS | 50 MSPS | 125 MSPS | 25 MSPS | 125 MSPS |
| Digital Interface | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B |
| Internal Dither | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- 4 channels at up to 160 MSPS in a single 48-VQFN 7x7 mm device （vs ADC32J44IRGZ25)
- Internal dither enabled in production silicon for high-linearity signals （vs Generic 14-bit quad ADCs without dither)
- JESD204B Subclass 0/1/2 with multi-chip synchronization support （vs Parallel LVDS quad ADCs in the same pin count)
設計ノート
The 48-VQFN (RGZ) package requires the exposed thermal pad to be soldered to a continuous ground copper pour with a thermal via array (typically 9 to 16 vias) for heat dissipation. Recommended input layout: matched-length differential traces (length matching to within 0.5 mm), 100-ohm differential impedance, and AC-coupling capacitors close to the AINP/AINN pins. The CLK+ and CLK- traces must be length-matched and isolated from the analog input traces to avoid digital feedback into the analog front end.
Use a low-jitter clock driver for the CLKP/CLKN input. Per the TI datasheet, every 1 ps of clock jitter degrades the SNR by approximately 1 dB at 70 MHz input; aim for under 200 fs RMS clock jitter to preserve the 72 dBFS SNR figure. The flexible divide-by-1, -2, -4 clock buffer lets you derive the ADC sample rate from a common reference oscillator across multiple boards.
Do not disable internal dither unless you have a system-level justification. Internal dither improves SFDR for high-input-frequency tones and the published 86 dBc SFDR is only achieved with dither enabled. The JESD204B link must be initialized through the SERDES register map per the datasheet; missing this step leaves the lanes in a non-functional state. Always validate the SYSREF timing relative to device clock per the JESD204B Subclass 1 setup-and-hold requirements.
Use separate analog (AVDD) and digital (DVDD) supply planes joined at a single point near the regulator. Decouple AVDD and DVDD each with a 1uF and a 0.1uF ceramic capacitor as close to the pins as possible. The 1.8 V single supply simplifies power tree design, but the input common-mode voltage (VCM) output must be buffered to drive the input driver op-amps to maintain DC bias accuracy.
コンプライアンス情報
RoHS compliant per TI product page. Industrial -40C to +85C temperature range; not AEC-Q100 qualified. For automotive grade, request the -Q1 suffix variant of the ADC34J4x family from TI.
