ADC34J25IRGZ25 - Quad 12-Bit 160MSPS ADC w/ JESD204B | Texas Instruments
部品番号: ADC34J25IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $39.5 | $39.50 |
| 10 | $35.55 | $355.50 |
| 100 | $30.2 | $3,020.00 |
| 500 | $26.85 | $13,425.00 |
| 1,000 | $24.1 | $24,100.00 |
ADC34J25IRGZ25 概要
The product type is a high-speed pipelined ADC. A pipelined analog-to-digital converter is a semiconductor device that converts continuous analog waveforms into discrete digital codes by sampling the input against a held reference through multiple low-resolution flash stages; it belongs to the broader category of data converters (which also includes successive-approximation, delta-sigma, and flash ADCs) within the integrated circuit family. Pipelined ADCs sit at the apex of speed-vs-resolution trade-offs and dominate the 50-500 MSPS range used in communications infrastructure, radar, and instrumentation.
Key features include a flexible input clock buffer with divide-by-1, -2, -4 options, an internal dither engine for improved small-signal linearity, a 105 dB channel-to-channel isolation, and ultra-low power consumption of 203 mW per channel at 160 MSPS. A JESD204B-compliant serial output interface (subclass 1) allows up to four ADCs to share a single high-speed digital lane back to an FPGA or ASIC.
Architecturally, the device uses four time-interleaved pipelined cores with on-chip input buffers, a shared bandgap reference (external reference supported), and an integrated digital processing block. Pin compatibility with the 14-bit ADC34J22 family allows drop-in migration when higher dynamic range is required without PCB rework.
Typical applications include wireless base-station receivers (multi-antenna MIMO), radar digitizers, medical imaging front-ends, and broadband test equipment. The device is well suited when synchronization across multiple channels and compact board area are required.
When designing with this ADC, plan input network termination to 50 ohms and provide low-jitter clocking; the JESD204B link requires deterministic latency, so use subclass 1 SYSREF for multi-device alignment. PCB stack-up should keep the analog and digital grounds separated until joined under the exposed pad.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.
ドロップイン代替品: ADC34J25IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC34J25IRGZ25 （同一形状・フットプリント） — 相違点: Package, Digital Interface, Operating Temperature, SNR, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
ADC34J22IRGZ25
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADC32J44IRGZ25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$42.1 / 個
データシートを見る →ADC3242IRGZ25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.4 / 個
データシートを見る →ADC3423IRTQ25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$21.85 / 個
データシートを見る →ADC34J25IRGZ25 最大定格＆電気的特性
| Manufacturer | Texas Instruments |
| Part Number | ADC34J25IRGZ25 |
| Number of Bits | 12 |
| サンプリングレート | 160 MSPS (max), 50 MSPS (min) |
| Number of Channels | 4 |
| Input Type | Differential |
| Data Interface | JESD204B |
| Configuration | ADC |
| Number of A/D Converters | 4 |
| Architecture | Pipelined |
| Reference Type | External |
| 電源電圧 | 1.8 V (nominal) |
| Power Consumption | 203 mW per channel at 160 MSPS |
| SNR | 69.6 dBFS at fIN = 70 MHz |
| SFDR | 86 dBc at fIN = 70 MHz |
| Channel Isolation | 105 dB |
| 動作温度 | -40°C to +85°C (industrial) |
| パッケージ | 48-VQFN (7x7 mm, RGZ) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADC34J25IRGZ25 ピン構成
| ピン 1 | AINP1 — Differential analog input positive, channel 1 |
| ピン 2 | AINN1 — Differential analog input negative, channel 1 |
| ピン 3 | AINP2 — Differential analog input positive, channel 2 |
| ピン 4 | AINN2 — Differential analog input negative, channel 2 |
| ピン 5 | AINP3 — Differential analog input positive, channel 3 |
| ピン 6 | AINN3 — Differential analog input negative, channel 3 |
| ピン 7 | AINP4 — Differential analog input positive, channel 4 |
| ピン 8 | AINN4 — Differential analog input negative, channel 4 |
| ピン 9 | GND — Ground |
| ピン 10 | VA11 — 1.8V analog supply |
| ピン 11 | VA12 — 1.8V analog supply |
| ピン 12 | VA18 — 1.8V analog supply |
| ピン 13 | GND — Ground |
| ピン 14 | CLKP — Differential clock input positive |
| ピン 15 | CLKN — Differential clock input negative |
| ピン 16 | GND — Ground |
| ピン 17 | SYSREFP — SYSREF positive (JESD204B subclass-1 reference) |
| ピン 18 | SYSREFN — SYSREF negative |
| ピン 19 | RESETn — Device reset (active low) |
| ピン 20 | CSn — SPI chip select (active low) |
| ピン 21 | SCLK — SPI serial clock |
| ピン 22 | SDIO — SPI serial data input/output |
| ピン 23 | SDOUT — SPI serial data output |
| ピン 24 | SEN — SPI enable |
| ピン 25 | GND — Ground |
| ピン 26 | VCM — Common-mode voltage output (for analog input biasing) |
| ピン 27 | VA11 — 1.8V analog supply |
| ピン 28 | VA12 — 1.8V analog supply |
| ピン 29 | VA18 — 1.8V analog supply |
| ピン 30 | GND — Ground |
| ピン 31 | REFP — External reference positive |
| ピン 32 | REFN — External reference negative |
| ピン 33 | GND — Ground |
| ピン 34 | VA11 — 1.8V analog supply |
| ピン 35 | VA18 — 1.8V analog supply |
| ピン 36 | GND — Ground |
| ピン 37 | VPHL — PHL supply for JESD204B I/O |
| ピン 38 | GND — Ground |
| ピン 39 | DA0P — JESD204B serial data lane 0 positive |
| ピン 40 | DA0N — JESD204B serial data lane 0 negative |
| ピン 41 | GND — Ground |
| ピン 42 | DA1P — JESD204B serial data lane 1 positive |
| ピン 43 | DA1N — JESD204B serial data lane 1 negative |
| ピン 44 | GND — Ground |
| ピン 45 | VA18 — 1.8V analog supply |
| ピン 46 | VPHL — PHL supply for JESD204B I/O |
| ピン 47 | GND — Ground |
| ピン 48 | NC — Not connected (per datasheet) |
| ピン 49 | EP — Exposed thermal pad - connect to GND |
主な用途
ADC34J25IRGZ25 の用途: 6 件s: Multi-Antenna Wireless Base Station Receiver, Phased-Array Radar Digitizer, Medical Ultrasound Imaging Front-End, Broadband Communications Test Equipment, Software Defined Radio (SDR) Platform, Industrial Motor Control Encoder Reader.
Multi-Antenna Wireless Base Station Receiver
The ADC34J25IRGZ25 fits 4G/5G base-station receivers because four 12-bit 160 MSPS channels consume only 203 mW each (total ~812 mW) yet deliver 69.6 dBFS SNR and 86 dBc SFDR. Per TI datasheet, the JESD204B subclass-1 interface deterministically aligns multiple ADCs across the antenna array, which is essential for MIMO demodulation. Engineers place the ADC between SAW filters and the FPGA baseband, set SYSREF for TDD-LTE/5G-NR frame alignment, and benefit from the 105 dB channel isolation to suppress cross-talk between diversity branches.
おすすめ
Phased-Array Radar Digitizer
Phased-array radar needs simultaneous multi-channel sampling at high SNR, and the ADC34J25IRGZ25's four pipelined cores at 160 MSPS satisfy this. The integrated dither engine randomizes quantization noise to maintain SFDR of 86 dBc even for small radar returns, while JESD204B subclass-1 determinism aligns pulse timings across the array. The 48-VQFN (RGZ) 7x7 mm package fits radar daughter-card thermal constraints when mounted on a continuous ground plane under the exposed pad.
おすすめ
Medical Ultrasound Imaging Front-End
Medical ultrasound beamformers typically need 32 to 128 channels of synchronized ADC sampling, and the ADC34J25IRGZ25's four channels per chip minimize board area. At 160 MSPS the ADC easily handles 40 MHz transducer bandwidth with 12-bit dynamic range. The JESD204B interface streams RF data to beamforming FPGAs with deterministic latency, and the 105 dB channel isolation prevents cross-coupling between adjacent transducer elements that would create image artifacts.
おすすめ
Broadband Communications Test Equipment
Vector signal analyzers and arbitrary waveform capture cards benefit from the ADC34J25IRGZ25's wide 50-160 MSPS range and four channels in one device. Engineers can digitize up to 70 MHz IF signals with 69.6 dBFS SNR, enough for EVM measurements on QAM-256 modulations. Pin compatibility with the 14-bit ADC34J22 family lets test-equipment vendors ship a single PCB that customers can upgrade to higher dynamic range later, reducing inventory SKU count.
おすすめ
Software Defined Radio (SDR) Platform
Wideband SDR receivers used for cellular baseband research need flexible multichannel sampling, and the ADC34J25IRGZ25 provides four simultaneous 160 MSPS ADCs in one 7x7 mm package. The JESD204B output feeds directly into a Zynq SoC for real-time DSP. Per TI reference designs, the input clock buffer supports divide-by-1, -2, -4, allowing designers to use a common reference clock across multiple chips at different rates for multi-band SDR captures.
おすすめ
Industrial Motor Control Encoder Reader
Multi-axis industrial servo drives need simultaneous multi-channel encoder and resolver-simulation feedback sampling, where the ADC34J25IRGZ25's four 160 MSPS ADC cores enable high-resolution position feedback. The JESD204B interface aggregates the four channels onto a single digital cable to the motion controller, reducing harness weight. Industrial -40°C to +85°C temperature rating and robust 1.8 V supply tolerance suit factory-floor vibration and EMI environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC34J25IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC34J22IRGZ25 | ADC32J44IRGZ25 | ADC3242IRGZ25 | ADC3423IRTQ25 | AD9629XCPZ-40 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Package | 48-VQFN (7x7 mm, RGZ) | 48-VQFN (7x7, RGZ) - same | 48-VQFN (7x7, RGZ) - same | 48-VQFN (7x7, RGZ) - same | 48-VQFN (7x7, RGZ) - same | 48-LFCSP (7x7) - same footprint |
| Resolution | 12-bit | 14-bit | 14-bit | 14-bit | 12-bit | 12-bit |
| Sample Rate | 160 MSPS | 160 MSPS | 125 MSPS | 50 MSPS | 80 MSPS | 40 MSPS |
| Channels | 4 | 4 | 4 | 2 | 4 | 1 |
| Data Interface | JESD204B | JESD204B | JESD204B | CMOS / LVDS | JESD204B | LVDS |
| Power per Channel | 203 mW/ch | ~250 mW/ch | ~300 mW/ch | ~150 mW/ch | ~95 mW/ch | ~175 mW/ch |
| SNR (at 70 MHz) | 69.6 dBFS | 72 dBFS | 74 dBFS | 75 dBFS | 69 dBFS | 70 dBFS |
| Operating Temperature | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C |
主な差別化要因
- Pin-compatible 14-bit upgrade path available （vs ADC34J22IRGZ25)
- Lower per-channel power than older TI quad ADCs （vs ADC32J44IRGZ25)
- JESD204B subclass-1 deterministic latency （vs ADC3242IRGZ25)
- Four independent differential inputs in 7x7 mm （vs AD9629XCPZ-40 (Analog Devices))
設計ノート
The ADC34J25IRGZ25 draws approximately 812 mW total at 160 MSPS across four channels from a single 1.8 V supply. Place 10 uF bulk ceramic plus 0.1 uF high-frequency decoupling within 5 mm of each VA11/VA12/VA18 pin, with a 2.2 uF ferrite-filtered rail if the rail also feeds a noisy FPGA. The exposed pad MUST be soldered to a continuous ground plane both for thermal dissipation (~31 C/W theta_JA) and to provide the reference ground for the internal ADC core.
Route differential analog inputs (AINP/AIN) with 100-ohm differential impedance and keep lengths matched to within 0.5 mm to preserve 86 dBc SFDR at full sample rate. JESD204B serial lanes (DA0P/N, DA1P/N) must use 100-ohm differential stripline or microstrip with length-matched traces - per TI JESD204B design guide, mismatches beyond 2 mm cause inter-symbol jitter that breaks the link at 5 Gbps. Place clock traces length-matched to within 0.13 mm.
Separate the analog ground plane (under pins 1-36) from the digital/clock ground plane (under pins 37-48), and join them at a single point under the exposed pad. The CLKP/CLKN and SYSREFP/N inputs are extremely noise-sensitive - route guard traces tied to analog ground and avoid crossing any high-speed digital traces. Use a Faraday-cage cutout around the reference pins (REFP/REFN) so external reference noise does not couple into the clock divider.
Provide a sub-300 fs RMS jitter clock source for the ADC clock input. Per TI datasheet, SNR degrades by approximately 20*log10(Tjitter/Tsample), so a 1 ps jitter yields only 56 dBFS SNR at 160 MSPS. Use a TCXO or dedicated clock synthesizer with careful power-supply decoupling - and ensure SYSREF has matched trace length to CLKP/N for deterministic latency in JESD204B subclass-1 mode.
Do not omit the external reference decoupling on REFP/REFN - 100 nF X7R right at the pins is mandatory for SFDR. Configure the SPI at boot to disable unused JESD204B lanes to save power. Do not exceed the absolute maximum analog input voltage (VA18 + 0.3 V) - downstream SAW filter transients can clip the input. Use the internal dither register (set via SPI) for improved small-signal linearity unless deterministic repeatability is required.
コンプライアンス情報
RoHS and REACH compliant per TI product page. Industrial -40°C to +85°C temperature grade. AEC-Q100 not applicable for this industrial/communications part - choose ADC34J25IRGZ25-Q1 (if available) for automotive. No SVHCs above 0.1% w/w declared.
