ADC34J44IRGZ25 - Quad 14-bit 125 MSPS ADC w/ JESD204B | Texas Instruments
部品番号: ADC34J44IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $152.91 | $152.91 |
| 10 | $137.62 | $1,376.20 |
| 100 | $122.33 | $12,233.00 |
| 250 | $114.68 | $28,670.00 |
| 500 | $107.04 | $53,520.00 |
ADC34J44IRGZ25 概要
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog voltage or current signals into discrete digital codes for downstream processing by FPGAs, ASICs, or microprocessors. The ADC34J44 belongs to the pipelined ADC subclass — the dominant architecture for sample rates between 1 MSPS and 1 GSPS — which uses a multi-stage cascaded architecture with residue amplification between stages to achieve high throughput. Within the broader IC taxonomy, this part sits as: ADC -> data converter -> mixed-signal IC -> semiconductor. The 'J' suffix in the part number denotes TI's high-speed JESD204B-interface family, a standardized serial link that simplifies multi-lane synchronization between data converters and logic devices.
Key features include an ultra-low power consumption of 203 mW per channel at 160 MSPS, a flexible input clock buffer supporting divide-by-1, -2, and -4, an internal dither engine for improved SFDR on small-signal inputs, and a JESD204B interface supporting Subclass 0, 1, and 2 deterministic latency with up to one lane per ADC. The 48-VQFN package with exposed pad provides a low thermal resistance path (θJA ~22 C/W) suitable for the device's modest power dissipation at 125 MSPS, eliminating the need for an external heatsink in most designs.
The device operates from a single 1.8 V supply and accepts differential analog inputs with a 1.0 Vpp full-scale range, with the input common-mode set internally to simplify board design. Multi-chip synchronization ( MCS ) is supported through the SYSREF and SYNC~ pins, enabling deterministic phase alignment across multiple ADC34J4x devices in phased-array, MIMO, or beam-forming systems. The internal dither circuit improves spurious-free dynamic range (SFDR) by 2-4 dB on small-signal inputs near the noise floor, which is critical for communications receivers where blocker signals may otherwise dominate.
Typical applications include multi-channel communications infrastructure (cellular base station receivers, software-defined radio, microwave backhaul), industrial imaging systems (medical ultrasound, non-destructive testing, machine vision), multi-channel data acquisition systems for test and measurement instrumentation, and defense electronics such as phased-array radar and electronic warfare systems. The combination of four synchronized channels on a single die reduces board area, BOM cost, and channel-to-channel mismatch in tightly-coupled systems.
When designing with the ADC34J44IRGZ25, route the JESD204B serial lanes as 100-Ω differential stripline/microstrip pairs with length matching within the lane (typically <0.5 mm) and across lanes (<6.25 UI per datasheet). Place decoupling capacitors as close as possible to each supply pin (1.0 µF ceramic plus 0.1 µF at the pin, plus bulk capacitance near the regulator), and provide a solid ground reference beneath the JESD204B traces. The internal dither must be enabled when the input signal can approach the -35 dBFS noise floor; disable only if downstream spectral purity is already adequate and you need to save 1-2 mW per channel.
This page synthesizes distributor pricing, pin-compatible same-family drop-in alternatives (ADC34J42IRGZ25, ADC34J25IRGZ25, ADC32J44IRGZ25), and practical JESD204B layout guidance that is not collected in a single location on the manufacturer datasheet — information gain that distributors and simple parametric search tools do not provide.
ドロップイン代替品: ADC34J44IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC34J44IRGZ25 （同一形状・フットプリント） — 相違点: Package, Number of Channels, Resolution, SNR, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
ADC34J42IRGZ25
✅ ドロップイン✓ 在庫あり
$52.1 / 個
データシートを見る →ADC34J25IRGZ25
✅ ドロップイン✓ 在庫あり
$24.1 / 個
データシートを見る →ADC32J44IRGZ25
✅ ドロップイン✓ 在庫あり
$42.1 / 個
データシートを見る →ADS62P48IRGC25
✅ ドロップイン✓ 在庫あり
$49.2 / 個
データシートを見る →ADS6129IRGZ25
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →ADS6242IRGZR
✅ ドロップイン✓ 在庫あり
$18.25 / 個
データシートを見る →ADC34J44IRGZ25 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 4 |
| Sample Rate | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Full-Scale Input Range | 1.0 Vpp |
| SNR (f_IN = 70 MHz) | 72 dBFS |
| SFDR (f_IN = 70 MHz) | 86 dBc |
| Channel-to-Channel Isolation | 105 dB |
| Power Consumption (per channel, 160 MSPS) | 203 mW |
| Digital Interface | JESD204B (Subclass 0/1/2) |
| Number of JESD204B Lanes | 1 per ADC (up to 160 MSPS) |
| 電源電圧 | 1.8 V (single supply) |
| Internal Dither | Yes |
| Multi-Chip Synchronization | Yes (SYSREF/SYNC~) |
| 動作温度範囲 | -40C to +85C (Industrial) |
| パッケージ | 48-VQFN (7x7 mm, RGZ) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADC34J44IRGZ25 ピン構成
| ピン 1 | IN1A — Channel 1 analog input, positive |
| ピン 2 | IN1B — Channel 1 analog input, negative (complement) |
| ピン 3 | AVDD — 1.8 V analog supply |
| ピン 4 | AVSS — Analog ground |
| ピン 5 | IN2A — Channel 2 analog input, positive |
| ピン 6 | IN2B — Channel 2 analog input, negative (complement) |
| ピン 7 | VCM — Internal common-mode voltage bypass |
| ピン 8 | AVDD — 1.8 V analog supply |
| ピン 9 | AVSS — Analog ground |
| ピン 10 | IN3A — Channel 3 analog input, positive |
| ピン 11 | IN3B — Channel 3 analog input, negative (complement) |
| ピン 12 | AVDD — 1.8 V analog supply |
| ピン 13 | AVSS — Analog ground |
| ピン 14 | IN4A — Channel 4 analog input, positive |
| ピン 15 | IN4B — Channel 4 analog input, negative (complement) |
| ピン 16 | AVDD — 1.8 V analog supply |
| ピン 17 | AVSS — Analog ground |
| ピン 18 | CLKP — Differential clock input, positive |
| ピン 19 | CLKN — Differential clock input, negative (complement) |
| ピン 20 | AVDD — 1.8 V analog supply |
| ピン 21 | AVSS — Analog ground |
| ピン 22 | SYSREF — JESD204B synchronization reference |
| ピン 23 | SYNC~ — JESD204B active-low synchronization request |
| ピン 24 | RESET — Hardware reset, active-low |
| ピン 25 | SCLK |
| ピン 26 | SDATA |
| ピン 27 | SEN~ |
| ピン 28 | GPIO — Multi-purpose digital I/O |
| ピン 29 | DRVDD — 1.8 V digital output supply |
| ピン 30 | DRVSS — Digital output ground |
| ピン 31 | DOUT0P — JESD204B lane 0, positive |
| ピン 32 | DOUT0N — JESD204B lane 0, negative (complement) |
| ピン 33 | DRVDD — 1.8 V digital output supply |
| ピン 34 | DRVSS — Digital output ground |
| ピン 35 | DOUT1P — JESD204B lane 1, positive |
| ピン 36 | DOUT1N — JESD204B lane 1, negative (complement) |
| ピン 37 | DRVDD — 1.8 V digital output supply |
| ピン 38 | DRVSS — Digital output ground |
| ピン 39 | DOUT2P — JESD204B lane 2, positive |
| ピン 40 | DOUT2N — JESD204B lane 2, negative (complement) |
| ピン 41 | DRVDD — 1.8 V digital output supply |
| ピン 42 | DRVSS — Digital output ground |
| ピン 43 | DOUT3P — JESD204B lane 3, positive |
| ピン 44 | DOUT3N — JESD204B lane 3, negative (complement) |
| ピン 45 | DVDD — 1.8 V digital core supply |
| ピン 46 | DVSS — Digital core ground |
| ピン 47 | AVDD — 1.8 V analog supply |
| ピン 48 | AVSS — Analog ground |
主な用途
ADC34J44IRGZ25 の用途: 6 件s: Multi-Channel Communications Receiver (Base Station / SDR), Medical Ultrasound Imaging Front-End, Multi-Channel Data Acquisition for Test & Measurement, Phased-Array Radar / Electronic Warfare, Industrial Multi-Channel Sensor Digitization, MIMO 5G / Wi-Fi Baseband Digitizer.
Multi-Channel Communications Receiver (Base Station / SDR)
The ADC34J44IRGZ25's four synchronized 14-bit, 125 MSPS channels are well-matched to multi-channel cellular base-station receivers, software-defined radio (SDR), and microwave backhaul links. Its 72 dBFS SNR and 86 dBc SFDR at 70 MHz input provide the linearity required for demodulating multi-carrier signals near full-scale, while the JESD204B Subclass 1 interface supports deterministic latency across multiple synchronized boards. Compared to a parallel-LVDS ADC of equivalent speed, this part reduces FPGA I/O pin count and PCB routing complexity. Typical deployment: 4-channel diversity receiver feeding an FPGA for digital downconversion and crest-factor reduction. Estimated power: ~640 mW total at 125 MSPS.
おすすめ
Medical Ultrasound Imaging Front-End
Medical ultrasound beamforming systems require dozens of synchronized analog input channels to digitize transducer arrays in real time. The ADC34J44IRGZ25's four channels and 105 dB channel-to-channel isolation support dense PCB layouts where channel-to-channel crosstalk directly degrades image contrast. Its 14-bit resolution and 72 dBFS SNR are adequate for low-MHz transducer frequencies (2-15 MHz), and the JESD204B interface enables deterministic-latency data transfer to the beamforming FPGA across long multi-board cabling. Designers commonly pair this ADC with a TI LMX2541 clock generator to provide the low-jitter clock required for high SFDR. Power consumption is favorable compared to discrete-ADC alternatives, simplifying thermal management in the hand-held probe.
おすすめ
Multi-Channel Data Acquisition for Test & Measurement
Automated test equipment (ATE), oscilloscopes, and spectrum analyzers benefit from the ADC34J44IRGZ25's four synchronized 125 MSPS ADCs in a single 48-VQFN package, allowing compact multi-channel input modules. The 72 dBFS SNR at 70 MHz and SFDR of 86 dBc support accurate measurement of bandwidth-limited signals up to ~62.5 MHz Nyquist. Internal dither improves SFDR on small-signal measurements near the noise floor by 2-4 dB — important when measuring filter stopband performance or EMC emissions. Designers add an external front-end amplifier (e.g. LMH6517 or THS4631) to scale input signals to the 1.0 Vpp full-scale range. The exposed thermal pad supports continuous full-speed acquisition without a heatsink.
おすすめ
Phased-Array Radar / Electronic Warfare
Phased-array radar systems and electronic-warfare (EW) receivers require dozens of tightly synchronized ADC channels with deterministic latency across multiple boards. The ADC34J44IRGZ25's multi-chip synchronization (SYSREF + SYNC~) plus JESD204B Subclass 1 deterministic latency enable sub-sample alignment of many channels in a single coherent receive aperture. The four channels per package minimize PCB area and channel-to-channel timing skew, while 105 dB isolation prevents strong interferers from coupling into adjacent channels. The 86 dBc SFDR provides the spur rejection needed to detect weak targets near large blockers. This ADC is typically paired with TI's LMX2582 wideband clock synthesizer for the low-jitter reference required by radar signal chains.
おすすめ
Industrial Multi-Channel Sensor Digitization
Industrial condition-monitoring systems — vibration analyzers, predictive-maintenance sensors, and multi-axis strain-gauge data loggers — often require 4-16 synchronized ADC channels per measurement node. The ADC34J44IRGZ25's four channels in a single package reduce BOM count and channel-to-channel timing error for vibration-phase comparison across axes. At 125 MSPS it oversamples 50 kHz vibration bandwidth by 2500x, allowing aggressive digital filtering to extract subtle fault signatures. The -40C to +85C industrial temperature grade and 1.8 V single-supply simplify power-tree design in factory-floor equipment. Industrial designers typically front-end this ADC with TI's INA128 instrumentation amplifier for bridge-style sensors.
おすすめ
MIMO 5G / Wi-Fi Baseband Digitizer
5G NR and Wi-Fi 7 MIMO radios require multiple synchronized ADC channels to digitize each spatial stream from the antenna front-end. The ADC34J44IRGZ25's four 125 MSPS channels fit a 4x4 MIMO receiver path sampling signals up to 62.5 MHz IF bandwidth, while the JESD204B interface streams raw samples directly to a 5G baseband FPGA or ASIC. The internal dither improves SFDR on small-signal carriers — critical for receivers operating near the sensitivity limit. MCS support ensures phase coherence across multiple ADC packages, enabling MIMO channel estimation algorithms to function correctly. Pair this ADC with a TI AFE7950 RF transceiver for a complete 4T4R small-cell radio chain.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC34J44IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC34J42IRGZ25 | ADC34J25IRGZ25 | ADC32J44IRGZ25 | ADS62P48IRGC25 | ADS6129IRGZ25 | ADS6242IRGZR |
|---|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 14 bit | 14 bit | 14 bit |
| Number of Channels | 4 | 4 | 2 | 2 | 2 | 1 | 2 |
| Sample Rate | 125 MSPS | 50 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS | 65 MSPS |
| Digital Interface | JESD204B | JESD204B | JESD204B | JESD204B | Parallel LVDS | Parallel LVDS | Parallel LVDS |
| Multi-Chip Synchronization | Yes (SYSREF/SYNC~) | Yes | Yes | Yes | No | No | No |
| Internal Dither | Yes | Yes | Yes | Yes | No | No | No |
主な差別化要因
- Four synchronized channels + JESD204B in a single 48-VQFN footprint （vs ADS62P48IRGC25)
- Higher sample rate with full pin-compatibility to lower-speed J4x family （vs ADC34J42IRGZ25)
- Built-in SYSREF multi-chip synchronization for phased arrays （vs ADS6242IRGZR)
設計ノート
Route the four JESD204B output lanes as 100-Ω differential pairs (microstrip or stripline) over a continuous ground reference plane. Match lengths within each lane to <0.5 mm and across lanes per the datasheet deterministic-latency specification (typically <6.25 UI). Place the AC-coupling capacitors as close as possible to the ADC transmit pins, and avoid routing the JESD204B lanes across any clock or analog signal trace to minimize crosstalk. Use a continuous reference-plane transition (no splits) under the lanes to maintain 100-Ω differential characteristic impedance.
Decouple every AVDD/DRVDD/DVDD pin individually with a 0.1 µF ceramic capacitor placed within 2 mm of the pin footprint, plus a 10 µF bulk capacitor at each supply rail entry point. Use a low-noise LDO regulator (such as TI's TPS7A47 or LP38851) to power the analog rails; switching regulator noise at the AVDD pin will directly couple into the analog input and degrade SNR by 5-10 dB. Keep the exposed thermal pad soldered to a continuous ground plane with at least 16 thermal vias to maintain the ~22 C/W θJA specified for continuous 125 MSPS operation.
Drive the analog inputs with a low-noise, low-jitter differential amplifier (such as TI's LMH6517 or THS4631) configured to provide the 1.0 Vpp full-scale input range and 0.95 V common-mode voltage expected by the ADC. Maintain 100-Ω differential impedance on the analog input traces up to the ADC pins, with length matching within 0.5 mm between A and B sides. The clock source must have <300 fs RMS jitter to achieve the datasheet SFDR; use a TI LMX2541 or LMX2582 clock synthesizer rather than a generic PLL.
Do not leave the SYSREF and SYNC~ pins floating; they must be tied to logic levels through proper JESD204B initialization. Forgetting to assert SYNC~ after configuration register changes will prevent link re-establishment and lead to silent data corruption. Also, when using the internal dither circuit, expect 1-2 LSB higher noise but 2-4 dB better SFDR on small-signal inputs — do not disable dither unless downstream SNR is already adequate and you have verified the trade-off.
コンプライアンス情報
RoHS and REACH compliance per TI product page. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified — choose a Q1-graded variant for automotive applications.
