ADS4245IRGC25 - 14-Bit 125MSPS Dual Low-Power ADC | Texas Instruments
部品番号: ADS4245IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.4 | $3,140.00 |
| 500 | $28.1 | $14,050.00 |
| 1,000 | $25.3 | $25,300.00 |
ADS4245IRGC25 概要
An analog-to-digital converter (ADC) is a data-conversion integrated circuit that samples continuous-time analog signals and produces discrete digital codes at a defined sample rate. Within the signal-chain hierarchy, an ADC sits between analog front-end conditioning (amplifiers, filters) and a digital processor (FPGA, DSP, ASIC). High-speed, moderate-resolution ADCs like the ADS4245 are typically deployed in IF/RF baseband digitizers, portable test equipment, and multi-channel imaging systems where low power and high channel density are required.
Key performance parameters include 125 MSPS maximum sample rate, 14-bit resolution, 82 dBFS SNR at 70 MHz input, 82 dBc SFDR, and a typical total power dissipation of 183 mW (CMOS) or 227 mW (DDR LVDS). The converter supports both external and internal reference modes, has 1.5 GHz analog input bandwidth, and a 1.8 V LVCMOS / DDR LVDS-compatible output interface. Industrial temperature range is -40C to +85C, and the part is supplied in a thermally enhanced VQFN-64 PowerPAD package.
The architecture is a pipelined switched-capacitor design with proprietary dithering to maintain SFDR at low input amplitudes. An integrated 2:1 input multiplexer supports two analog channels, and a serial control interface (SPI/parallel) provides access to internal registers for gain, offset, and test-pattern configuration. The internal reference (1.5 V) is factory-trimmed to within +/-2% across the operating range, simplifying PCB design and reducing the external BOM.
Typical applications include wireless communication baseband digitizers, handheld and portable test equipment, multi-channel data acquisition systems, radar and lidar intermediate-frequency processing, and medical imaging front ends. The dual-channel, low-power profile makes the ADS4245 particularly well-suited to space-constrained or battery-powered systems.
When designing with this part, route the analog inputs as 50-ohm-controlled differential traces, decouple the AVDD pins with 0.1 uF and 10 uF ceramic capacitors placed within 2 mm of each supply pin, and stitch the VQFN exposed pad to a continuous ground plane to meet the 31 C/W junction-to-ambient thermal resistance.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB / thermal design notes not found in the manufacturer datasheet, providing engineers a single reference for sourcing and implementing the ADS4245IRGC25.
ドロップイン代替品: ADS4245IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS4245IRGC25 （同一形状・フットプリント） — 相違点: Input Type, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
ADS4245IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS4246IRGC25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS4225IRGC25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS4245IRGCR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS62P48IRGC25
✅ ドロップイン✓ 在庫あり
$49.2 / 個
データシートを見る →ADS4245IRGC25 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (Max) | 125 MSPS |
| Input Type | Differential, analog |
| Architecture | Pipelined |
| Supply Voltage (AVDD) | 1.8 V |
| Digital Output Interface | CMOS (default) / DDR LVDS (optional) |
| Analog Input Bandwidth | 1.5 GHz (typical) |
| SNR at 70 MHz Input | 82 dBFS |
| SFDR at 70 MHz Input | 82 dBc |
| Total Power at 125 MSPS (CMOS) | 183 mW |
| Total Power at 125 MSPS (DDR LVDS) | 227 mW |
| Internal Reference | Yes (factory-trimmed, +/-2%) |
| 動作温度範囲 | -40C to +85C (industrial) |
| パッケージ | 64-VQFN (9x9 mm) with PowerPAD |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Control Interface | Serial (SPI-compatible) / parallel |
ADS4245IRGC25 ピン構成
| ピン 1 | INB_N — Channel B analog input negative (differential) |
| ピン 2 | INB_P — Channel B analog input positive (differential) |
| ピン 3 | AVDD — 1.8 V analog supply |
| ピン 4 | AVDD — 1.8 V analog supply |
| ピン 5 | GND — Ground |
| ピン 6 | GND — Ground |
| ピン 7 | INA_N — Channel A analog input negative (differential) |
| ピン 8 | INA_P — Channel A analog input positive (differential) |
| ピン 9 | AVDD — 1.8 V analog supply |
| ピン 10 | GND — Ground |
| ピン 11 | REFT — Reference decoupling top (internal reference) |
| ピン 12 | REFB — Reference decoupling bottom (internal reference) |
| ピン 13 | AVDD — 1.8 V analog supply |
| ピン 14 | GND — Ground |
| ピン 15 | SCLK — Serial interface clock |
| ピン 16 | SDATA — Serial interface data |
| ピン 17 | SEN — Serial interface enable |
| ピン 18 | SDOUT — Serial interface data output |
| ピン 19 | GND — Ground |
| ピン 20 | RESET — Hardware reset (active low) |
| ピン 21 | PDN — Power-down (active high) |
| ピン 22 | AVDD — 1.8 V analog supply |
| ピン 23 | GND — Ground |
| ピン 24 | CLK_N — Differential clock input negative |
| ピン 25 | CLK_P — Differential clock input positive |
| ピン 26 | GND — Ground |
| ピン 27 | DRVDD — 1.8 V digital output supply |
| ピン 28 | DRGND — Digital output ground |
| ピン 29 | D0A — Channel A data output bit 0 (LSB) |
| ピン 30 | D1A — Channel A data output bit 1 |
| ピン 31 | D2A — Channel A data output bit 2 |
| ピン 32 | D3A — Channel A data output bit 3 |
| ピン 33 | D4A — Channel A data output bit 4 |
| ピン 34 | D5A — Channel A data output bit 5 |
| ピン 35 | D6A — Channel A data output bit 6 |
| ピン 36 | D7A — Channel A data output bit 7 |
| ピン 37 | D8A — Channel A data output bit 8 |
| ピン 38 | D9A — Channel A data output bit 9 |
| ピン 39 | D10A — Channel A data output bit 10 |
| ピン 40 | D11A — Channel A data output bit 11 |
| ピン 41 | D12A — Channel A data output bit 12 |
| ピン 42 | D13A — Channel A data output bit 13 (MSB) |
| ピン 43 | DRGND — Digital output ground |
| ピン 44 | DRVDD — 1.8 V digital output supply |
| ピン 45 | D0B — Channel B data output bit 0 (LSB) |
| ピン 46 | D1B — Channel B data output bit 1 |
| ピン 47 | D2B — Channel B data output bit 2 |
| ピン 48 | D3B — Channel B data output bit 3 |
| ピン 49 | D4B — Channel B data output bit 4 |
| ピン 50 | D5B — Channel B data output bit 5 |
| ピン 51 | D6B — Channel B data output bit 6 |
| ピン 52 | D7B — Channel B data output bit 7 |
| ピン 53 | D8B — Channel B data output bit 8 |
| ピン 54 | D9B — Channel B data output bit 9 |
| ピン 55 | D10B — Channel B data output bit 10 |
| ピン 56 | D11B — Channel B data output bit 11 |
| ピン 57 | D12B — Channel B data output bit 12 |
| ピン 58 | D13B — Channel B data output bit 13 (MSB) |
| ピン 59 | DRGND — Digital output ground |
| ピン 60 | DRVDD — 1.8 V digital output supply |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | AVDD — 1.8 V analog supply |
| ピン 64 | GND — Ground |
| ピン DAP | EPAD — Exposed thermal pad - must be soldered to ground plane for 31 C/W theta_JA |
主な用途
ADS4245IRGC25 の用途: 6 件s: Wireless Baseband Digitizer, Handheld and Portable Test Equipment, Multi-Channel Data Acquisition System, Radar / Lidar IF Signal Processing, Medical Imaging Front End (Ultrasound / PET), Communications Test & Measurement (IQ Modem Tester).
Wireless Baseband Digitizer
The ADS4245IRGC25 is well matched to multi-channel wireless baseband digitization in small-cell, repeater, and software-defined radio designs. Its dual 125 MSPS channels, 1.5 GHz analog input bandwidth, and 82 dBFS SNR at 70 MHz let engineers digitize a 20 MHz LTE signal with more than 70 dB of usable dynamic range, while the 183 mW total power keeps the 4x4 MIMO thermal budget manageable. The internal 1.5 V reference and single 1.8 V supply minimize bill-of-materials. The VQFN-64 9x9 mm footprint is well suited to mezzanine cards where 4+ channels must fit in a 30x30 mm area. Designers typically pair it with a TI LMH6522 dual DVGA upstream and a Xilinx Artix-7 or Lattice ECP5 downstream for cost-sensitive multi-antenna receivers.
おすすめ
Handheld and Portable Test Equipment
The ADS4245IRGC25's 183 mW total power and 1.8 V single supply make it a strong fit for battery-powered oscilloscopes, spectrum analyzers, and signal-integrity probes. The 1.5 GHz analog input bandwidth supports undersampling of 1 GHz IF signals, eliminating a down-conversion stage, while the dual-channel architecture enables two simultaneous scope channels from a single IC. The 82 dBc SFDR guarantees clean dynamic range for spectral measurements. The industrial -40C to +85C operating range ensures reliable operation across factory-floor and field environments. The VQFN-64 PowerPAD provides low thermal resistance for sealed enclosures with no forced-air cooling, and the internal reference removes the need for a precision external reference that would otherwise consume board area.
おすすめ
Multi-Channel Data Acquisition System
Multi-channel industrial DAQ and acoustic-beamforming systems benefit from the ADS4245's dual-channel integration, low power, and 14-bit resolution. Two simultaneous 125 MSPS samples per IC cut the per-channel cost below that of single-channel ADCs while maintaining 82 dBFS SNR. The internal reference and small 9x9 mm VQFN footprint allow high channel density on a single board, supporting 8+ channels in 4 square inches. The CMOS or DDR LVDS output interface provides flexibility to drive either low-cost FPGAs (CMOS) or noise-immune backplanes (LVDS) over longer traces. Industrial temperature grade (-40C to +85C) and proven TI ultralow-power silicon make it a reliable choice for factory instrumentation, sonar arrays, and phased-array microphone systems.
おすすめ
Radar / Lidar IF Signal Processing
The ADS4245IRGC25 is widely used in radar and lidar intermediate-frequency digitization, where its 1.5 GHz input bandwidth and 82 dBc SFDR let designers sample 100-200 MHz IF signals directly with excellent spurious-free dynamic range. The dual-channel architecture supports simultaneous I/Q sampling of a single IF channel, simplifying I/Q imbalance calibration. Power consumption of 183 mW is low enough to deploy in phased-array radar sub-arrays that must stay within tight thermal envelopes, while the VQFN-64 package provides a low 31 C/W thermal resistance for sealed RF front-end enclosures. The internal reference removes a thermal-noise source that would otherwise degrade close-in dynamic range, critical for detecting small moving targets in the presence of large stationary clutter.
おすすめ
Medical Imaging Front End (Ultrasound / PET)
In ultrasound beamformers and PET detector front ends, the ADS4245IRGC25's dual-channel integration and 82 dBFS SNR are excellent for digitizing the output of multichannel preamps without sacrificing channel density. The 14-bit resolution at 125 MSPS meets the dynamic range required for low-contrast lesion detection in B-mode ultrasound, while the 183 mW per dual-channel power keeps the hundreds-of-channels system thermal load manageable. The internal reference and small 9x9 mm VQFN allow 64+ channels on a single 6-layer board. The industrial temperature range and TI's long-term product lifecycle support (>10 years) align with medical equipment certification cycles. Designers typically pair it with TI AFE5808A or THS4631 preamps and a TI KeyStone DSP or Xilinx Zynq Ultrascale processor.
おすすめ
Communications Test & Measurement (IQ Modem Tester)
The ADS4245IRGC25 is ideal for production-test equipment that needs to digitize I/Q modulator output, demodulated IF, or error-vector-magnitude (EVM) test signals. The dual-channel architecture is a natural fit for direct I/Q sampling at baseband or low IF, while the 82 dBFS SNR at 70 MHz supports measurement of 1024-QAM constellations with more than 40 dB of EVM headroom. The 1.5 GHz analog bandwidth allows direct sampling of L-band IF signals without a down-conversion stage, simplifying the tester architecture. The 183 mW power and small 9x9 mm VQFN enable high-density PXI / PXIe / LXI tester modules, and the CMOS output interface can directly drive a low-cost FPGA for real-time DSP. The industrial -40C to +85C range ensures calibration stability across production-floor temperature variations.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS4245IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS4245IRGCT | ADS4246IRGC25 | ADS4225IRGC25 | ADS4245IRGCR | ADS62P48IRGC25 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (9x9) | VQFN-64 (9x9) - same | VQFN-64 (9x9) - same | VQFN-64 (9x9) - same | VQFN-64 (9x9) - same | VQFN-64 (9x9) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 14 bit | 14 bit |
| Sample Rate (Max) | 125 MSPS | 125 MSPS | 160 MSPS | 125 MSPS | 125 MSPS | 200 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Power at Max Speed (CMOS) | 183 mW | 183 mW | 220 mW | 160 mW | 183 mW | 380 mW |
| SNR at 70 MHz | 82 dBFS | 82 dBFS | 82 dBFS | 71 dBFS | 82 dBFS | 84 dBFS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes | Yes |
| Output Interface | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
主な差別化要因
- Lowest power in the ADS424x family at 125 MSPS （vs ADS62P48IRGC25)
- Higher SNR than the 12-bit ADS4225IRGC25 （vs ADS4225IRGC25)
- Identical pinout to ADS4246 upgrade path （vs ADS4246IRGC25)
設計ノート
Decouple each AVDD pin with a 0.1 uF X7R ceramic placed within 2 mm, plus a 10 uF bulk capacitor on the analog supply plane. Separate AVDD and DRVDD planes should join only at one point near the IC to prevent digital switching noise from coupling into the analog front-end. The 1.8 V LDO powering DRVDD should have its own ferrite bead filter to keep switching noise below 1 mVrms, which is critical for meeting 82 dBFS SNR.
Estimated: at 125 MSPS CMOS output mode, the ADS4245IRGC25 dissipates 183 mW, and the VQFN-64 PowerPAD has a theta_JA of 31 C/W. Junction temperature rise above ambient is therefore 183 mW x 31 C/W = 5.7 C, well within the 125 C maximum. For sealed enclosures with no forced-air cooling, ensure the PCB has at least 4 square cm of 1 oz copper connected to the exposed pad, and solder the EPAD with a 4x4 thermal via array to the internal ground plane.
Route analog input traces as 50-ohm-controlled differential pairs with constant 100-ohm differential impedance, length-matched to within 0.5 mm. Keep CLK_P and CLK_N traces length-matched and isolated from the analog inputs by at least 3 trace widths to avoid clock-coupling spurs. Stitch the ground plane with vias on a 5 mm pitch around the IC perimeter, and do not route digital output traces (D0A-D13A) under the analog input section. For DDR LVDS output mode, route the LVDS pairs as 100-ohm differential and match within 0.1 mm.
Do not float the SEN pin at power-up; tie it high via a 10 kohm pull-up to DRVDD to keep the serial interface in a known state. Do not exceed 2.0 V on AVDD or DRVDD - the part is not 3.3 V tolerant. Avoid using the internal reference mode in systems with significant temperature transients (>20 C swing) if absolute full-scale accuracy below 1% is required; in that case, switch to external reference mode and use a precision ADR01 or REF198. Finally, do not apply analog input signals before powering up the AVDD supply, as this can permanently damage the input ESD structure.
コンプライアンス情報
RoHS and lead-free per TI product page. Industrial temperature grade (-40C to +85C), not AEC-Q100 qualified for automotive. Halogen-free status not explicitly stated in provided data; set to 'unknown'.
