DSPIC33EP128GM604T-I/ML - 70 MIPS 16-bit DSC, 128KB Flash | Microchip
部品番号: DSPIC33EP128GM604T-I/ML ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.84 | $6.84 |
| 10 | $6.16 | $61.60 |
| 100 | $5.5 | $550.00 |
| 500 | $4.95 | $2,475.00 |
| 1,000 | $4.4 | $4,400.00 |
DSPIC33EP128GM604T-I/ML 概要
A digital signal controller combines the computational core of a microcontroller with DSP-style multiply-accumulate hardware, single-cycle MAC, and DSP addressing modes. Within the power-management hierarchy of embedded processors, a DSC sits between general-purpose MCUs and dedicated DSPs, making it the natural choice for closed-loop control systems that need both fast math and deterministic I/O behavior.
Key differentiating features include twelve motor-control PWM channels (12 MCPWM) with complementary outputs and dead-time control, eight input capture and eight output capture/compare channels, two quadrature encoder interfaces (QEI), four integrated operational amplifiers, a Charge Time Measurement Unit (CTMU) for capacitive touch and precision timing, and a Pattern Generator (PTG) for autonomous sequencing. A Controller Area Network (CAN) module supports automotive and industrial networking.
The dsPIC33EP core is pipelined and engineered for single-cycle DSP instructions at 70 MIPS, allowing FOC (field-oriented control) loops and digital filters to execute well within PWM periods. Flexible clocking with internal PLL removes the need for an external crystal in cost-sensitive designs.
Typical applications include brushless DC and PMSM motor drives, digital power conversion (PFC, LLC), sensorless FOC compressors, and industrial automation nodes that combine CAN communication with real-time control.
For design, decouple all VDD/VDDCORE pins with 0.1uF ceramics placed at the pin, and budget Flash/RAM margins before selecting the 128KB density versus the 64KB/256KB family members in the same 44-QFN footprint.
This page synthesizes distributor pricing tiers, drop-in family alternatives, design notes, and comparison data not consolidated in the manufacturer datasheet.
ドロップイン代替品: DSPIC33EP128GM604T-I/ML — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33EP128GM604T-I/ML （同一形状・フットプリント） — 相違点: Package, Core, Operating Temperature, Input Capture / Output Compare, Packaging.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33EP128GM604-I/ML
✅ ドロップイン✓ 在庫あり
$5.95 / 個
データシートを見る →DSPIC33EP128GM304T-I/ML
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.62 / 個
データシートを見る →DSPIC33EP256GM604T-I/ML
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.98 / 個
データシートを見る →DSPIC33EP64GM604T-I/ML
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EP128GM604-I/PT
✅ ドロップイン✓ 在庫あり
$3.88 / 個
データシートを見る →DSPIC33EP128GM604T-I/ML 最大定格＆電気的特性
| Core | 16-bit dsPIC33EP DSC |
| Maximum CPU Speed | 70 MIPS |
| Program Memory Size | 128 KB (43K x 24) Flash |
| RAM Size | 16 KB |
| Motor Control PWM Channels | 12 MCPWM |
| Input Capture / Output Compare | 8 IC / 8 OC |
| Quadrature Encoder Interfaces | 2 QEI |
| On-chip Operational Amplifiers | 4 |
| Charge Time Measurement Unit | CTMU (yes) |
| Pattern Generator | PTG (yes) |
| CAN Module | Yes |
| 動作温度範囲 | -40C to +85C (I grade) |
| パッケージ | 44-QFN (ML) |
| 実装タイプ | Surface Mount |
| Packaging | Tape & Reel (T suffix) |
| RoHS ステータス | Compliant |
DSPIC33EP128GM604T-I/ML 44-qfn (ml) ピン配置ガイド
DSPIC33EP128GM604T-I/ML (44-qfn (ml) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33EP128GM604T-I/ML.
詳細は データシート をご参照ください。
主な用途
DSPIC33EP128GM604T-I/ML の用途: 6 件s: BLDC / PMSM Motor Drives, Digital Power Conversion, Industrial Automation Nodes, HVAC Compressor Control, Capacitive Touch and Measurement Interfaces, Signal Processing and Sensor Conditioning.
BLDC / PMSM Motor Drives
The DSPIC33EP128GM604T-I/ML is purpose-built for precision motor control: its 12 motor-control PWM channels provide complementary outputs with hardware dead-time insertion, the two quadrature encoder interfaces accept position feedback directly, and the four on-chip op-amps amplify low-level shunt-resistor current signals without external amplifier ICs. The 70 MIPS DSP core executes field-oriented control (FOC) loops well within one PWM period, enabling sensorless or sensored drives for pumps, fans, compressors, and servo axes. Placed between the gate-driver input network and the current-sense shunts, the DSC digitizes phase currents each PWM cycle through its ADC; the main trade-off versus a dedicated ASIC is firmware development effort, repaid by full flexibility across motor types and power stages.
おすすめ
Digital Power Conversion
In digital power supplies - PFC stages, LLC resonant converters, and bidirectional DC-DC chargers - the DSPIC33EP128GM604T-I/ML closes fast voltage and current loops in firmware using its 70 MIPS single-cycle MAC engine for the compensator math. The 12 MCPWM channels generate phase-shifted or complementary PWM with programmable dead time, essential for half-bridge and full-bridge topologies, while the CTMU supports precise time measurements for zero-crossing detection. Typical use places the DSC between the voltage/current sense dividers and the gate drivers, sampling each switching cycle; because the control law is firmware-defined, one PCB can be retuned across output voltages. The key design consideration is ADC-to-PWM latency budgeting, which the high core speed helps minimize.
おすすめ
Industrial Automation Nodes
For industrial automation endpoints - conveyor controllers, actuator drivers, and machine sub-modules - the DSPIC33EP128GM604T-I/ML combines a hardware CAN (ECAN) module with the motor-control and capture peripherals needed for local real-time behavior. The ECAN interface connects the node to factory fieldbuses through a transceiver, while 8 input captures and 8 output compares handle encoder, ultrasonic, and timing-critical I/O locally without burdening a supervisory PLC. The PTG (pattern generator) autonomously sequences peripherals in hardware, offloading the CPU. Typical deployments run the DSC at 70 MIPS from an internal PLL, -40C to +85C industrial rating covering cabinet environments; the trade-off versus an MCU-plus-FPGA split is lower cost and simpler single-chip firmware maintenance.
おすすめ
HVAC Compressor Control
Variable-speed HVAC and refrigeration compressors use sensorless FOC, and the DSPIC33EP128GM604T-I/ML fits this role with its 4 on-chip op-amps for three-shunt current sensing, 12 MCPWM channels for the inverter bridge, and 70 MIPS of DSP headroom for sliding-mode or MRAS rotor-position observers. Operating from the industrial -40C to +85C range, the controller processes phase currents each PWM cycle and adjusts the space-vector modulation output in real time, improving seasonal efficiency versus fixed-speed compressors. The CTMU can also support capacitive-touch user interfaces on the same chip. Design consideration: provide adequate heatsinking/copper for the QFN thermal pad and filter the op-amp inputs against switching noise from the IGBT bridge.
おすすめ
Capacitive Touch and Measurement Interfaces
The CTMU (Charge Time Measurement Unit) on the DSPIC33EP128GM604T-I/ML enables capacitive-touch keys and precision time-interval or resistance measurement without a dedicated touch controller. Combined with the 70 MIPS core for debounce and multi-key gesture processing, a single 44-QFN DSC can run a machine's HMI (touch slider, buttons) while simultaneously controlling a motor or power stage on the same silicon. The CTMU's constant-current charge method supports capacitive sensing and, per the family datasheet, time-domain measurement applications; 16KB of RAM buffers scan results and running averages. The main design consideration is electrode PCB layout and grounding discipline so switching-noise from co-resident PWM outputs does not couple into touch sense lines.
おすすめ
Signal Processing and Sensor Conditioning
With single-cycle MAC, DSP addressing modes, and four integrated op-amps, the DSPIC33EP128GM604T-I/ML performs front-end signal conditioning and real-time DSP - FIR/IIR filtering, RMS computation, FFT-based diagnostics - directly on 16-bit sensor data. The op-amps can be configured as programmable-gain amplifiers ahead of the ADC, removing external amplifier stages in vibration, acoustic, and current-signature monitoring products. At 70 MIPS the core sustains meaningful sampling-and-filter throughput at kilohertz-to-tens-of-kilohertz rates, while 128KB Flash holds both the DSP code and communication stacks. Typical architecture: sensor -> on-chip op-amp gain stage -> ADC -> firmware filter -> CAN/UART output. Trade-off versus an external DSP is modest numeric throughput, offset by integration and BOM reduction.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33EP128GM604T-I/ML — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33EP128GM604-I/ML | DSPIC33EP128GM304T-I/ML | DSPIC33EP256GM604T-I/ML | DSPIC33EP64GM604T-I/ML |
|---|---|---|---|---|---|
| Package | 44-QFN (ML) | 44-QFN (ML) - same | 44-QFN (ML) - same | 44-QFN (ML) - same | 44-QFN (ML) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS |
| Flash Program Memory | 128 KB (43K x 24) | 128 KB | 128 KB | 256 KB | 64 KB |
| Motor Control PWM | 12 MCPWM | 12 MCPWM | 12 MCPWM | 12 MCPWM | 12 MCPWM |
| On-chip Op-Amps | 4 | 4 | Fewer than GM604 | 4 | 4 |
| Packaging Format | Tape & Reel (T suffix) | Tube / Cut Tape | Tape & Reel | Tape & Reel | Tape & Reel |
主な差別化要因
- Four on-chip operational amplifiers for current sensing （vs DSPIC33EP128GM304T-I/ML)
- 256KB Flash upgrade in the identical footprint （vs DSPIC33EP256GM604T-I/ML)
- Best value if 64KB suffices （vs DSPIC33EP64GM604T-I/ML)
- Tape-and-reel production packaging （vs DSPIC33EP128GM604-I/ML)
設計ノート
The dsPIC33EP core requires a stable VDDCORE supply - follow the family datasheet's mandatory minimum pin connections list (VDD, VSS, VDDCORE capacitor, MCLR pull-up, AVDD/AVSS) exactly, as stated in document 70000689. Place a 0.1uF ceramic capacitor within 2 mm of every VDD pin and a bulk 10uF per power domain. Estimated: a 70 MIPS dsPIC33EP draws on the order of tens of milliamps - budget supply rails with margin for peripheral loads (CAN transceiver ~ up to 50 mA) on the shared 3.3V rail.
The 44-QFN (ML) has a central exposed pad that must be soldered to a grounded or appropriately tied thermal array - verify the die-pad connection requirement in the family datasheet before finalizing the footprint. For the four on-chip op-amps used with shunt current sensing, route the shunt Kelvin connections directly to the op-amp input pins, keep the loops small, and guard the analog traces away from MCPWM output lines. Use 1oz copper with a solid ground plane; QFN peripheral pads benefit from via stitching to the plane for both thermal and signal-integrity reasons.
Three frequent mistakes with the GM6xx family: (1) forgetting that most digital pins are remappable via Peripheral Pin Select (PPS) - lock the PPS mapping early in firmware and document it against the schematic; (2) assuming analog pins are remappable - op-amp and ADC inputs are fixed, so the schematic must match the fixed analog pin map; (3) ignoring the ERRATA/clarification documents when picking a Flash revision - always download errata from the Microchip product page alongside datasheet 70000689. Also budget Flash margin: 128KB fills quickly with CAN stacks plus FOC math.
Estimated: at typical DSC currents (tens of mA at 3.3V, roughly 0.15W), a 44-QFN with a solid ground-plane copper pour keeps junction temperature well below the +125C absolute limit even at +85C ambient. Thermal risk only becomes relevant when co-located drivers or regulators dissipate onto shared copper - separate gate-driver heat paths from the MCU zone, and verify the package theta-JA value in the family datasheet rather than assuming QFN-44 generic figures.
コンプライアンス情報
RoHS compliant per Microchip product status for standard-production parts. REACH, halogen-free and conflict-minerals declarations should be confirmed on the official Microchip product page environmental documentation.
