EP1810LC-20 - 900-Gate Classic EPLD, 48 Macrocells, 20ns | Intel
部品番号: EP1810LC-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $7.85 | $7,850.00 |
EP1810LC-20 概要
An EPLD is an Erasable Programmable Logic Device - a member of the programmable logic hierarchy that sits between discrete PAL/GAL devices and modern CPLDs. Within the broader taxonomy it is a complex PLD that combines multiple PAL-like AND/OR arrays with a configurable macrocell fabric. Classic EPLDs were the predecessors to today's CPLDs, offering non-volatile, instant-on configuration, deterministic timing, and high drive capability - characteristics still valued in glue logic, bus interface, and state-machine replacement applications.
Key features of the EP1810LC-20 include 48 macrocells interconnected by global and local buses, 12 dedicated inputs, and a maximum toggle frequency of 50 MHz. The device provides bi-directional I/O pins with user-configurable output enable polarity, programmable macrocell flip-flops with D, T, JK, and SR modes, and 100% generically testable logic. Power dissipation is low for a 5 V CMOS EPLD, and the part supports ISP (In-System Programmability) on selected variants via the Altera programming algorithm.
The architecture integrates a programmable AND array feeding a fixed OR array, the classic sum-of-products realization that made the Classic family attractive for state-machine and decoder logic. Each macrocell contains a programmable flip-flop, output polarity selection, and feedback path so that registered or combinatorial outputs can be routed back into the AND plane - enabling dense sequential designs in a single device.
Typical applications for the EP1810LC-20 include address decoding and glue logic in legacy 5 V systems, peripheral interface controllers for ISA/VME/Motorola bus architectures, state machines in industrial controllers, and pin-compatible replacements for discrete 74LS/74S TTL logic. The device is well suited to long-life-cycle industrial, military, and avionics programs where the part's 25+ year production track record is more important than raw density.
When designing with the EP1810LC-20, ensure all inputs are within TTL thresholds for the 5 V interface and place decoupling capacitors (0.1 uF per VCC pin group) close to the package. The Classic family's deterministic timing model (tPD 20 ns, tCO 15 ns, tSU 15 ns) allows static timing analysis without place-and-route iterations, which is a significant advantage over modern SRAM-based FPGAs for safety-critical designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EP1810LC-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1810LC-20 （同一形状・フットプリント） — 相違点: Package, Technology, Mounting Type, Operating Temperature, Device Type.
クイック比較ツール — 並列比較する代替部品を選択:
EP1810LC-25
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.4 / 個
データシートを見る →EP1810LC-15
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP1810LC-20T
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.95 / 個
データシートを見る →EP1810LC-30
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.95 / 個
データシートを見る →EP1810LC-45
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$49.9 / 個
データシートを見る →EP1810JI-45
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EP1810LC-20 最大定格＆電気的特性
| Family | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 |
| Macrocells | 48 |
| Maximum Operating Frequency | 50 MHz |
| Propagation Delay (tPD) | 20 ns |
| 電源電圧 | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM |
| Programmability | UV-Erasable / OTP |
| Dedicated Inputs | 12 |
| パッケージ | 68-pin PLCC |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | 20 ns (commercial) |
| 動作温度 | 0C to +70C (commercial) |
| 実装タイプ | Surface Mount |
EP1810LC-20 ピン構成
| ピン 1 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 2 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 3 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 4 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 5 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 6 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 7 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 8 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 9 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 10 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 11 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 12 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 13 | INPUT — Dedicated input pin |
| ピン 14 | INPUT — Dedicated input pin |
| ピン 15 | INPUT — Dedicated input pin |
| ピン 16 | INPUT — Dedicated input pin |
| ピン 17 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 18 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 19 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 20 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 21 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 22 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 23 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 24 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 25 | GND — Ground |
| ピン 26 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 27 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 28 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 29 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 30 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 31 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 32 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 33 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 34 | INPUT — Dedicated input pin |
| ピン 35 | INPUT — Dedicated input pin |
| ピン 36 | INPUT — Dedicated input pin |
| ピン 37 | INPUT — Dedicated input pin |
| ピン 38 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 39 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 40 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 41 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 42 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 43 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 44 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 45 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 46 | VCC — +5V supply |
| ピン 47 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 48 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 49 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 50 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 51 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 52 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 53 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 54 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 55 | INPUT — Dedicated input pin |
| ピン 56 | INPUT — Dedicated input pin |
| ピン 57 | INPUT — Dedicated input pin |
| ピン 58 | INPUT — Dedicated input pin |
| ピン 59 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 60 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 61 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 62 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 63 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 64 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 65 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 66 | I/O — Bidirectional I/O pin (macrocell controlled) |
| ピン 67 | GND — Ground |
| ピン 68 | VCC — +5V supply |
主な用途
EP1810LC-20 の用途: 6 件s: Legacy 5V Glue Logic Replacement, ISA/VME Bus Address Decoder, Industrial State Machine Controller, Peripheral Interface Controller, Pin-Compatible TTL Replacement, Long-Life-Cycle Military/Avionics Sustaining.
Legacy 5V Glue Logic Replacement
The EP1810LC-20 replaces dense clusters of 74LS/74ALS/74F TTL glue logic with a single non-volatile device, simplifying PCB layout and reducing BOM count in legacy 5V systems. Its 48 macrocells and deterministic 20 ns tPD (Altera Classic datasheet) absorb address decoding, chip-select generation, and bus-control logic that previously required dozens of discrete gates. The 900 usable gates (per Altera spec) consolidate entire decode trees into one PLCC-68 part. Engineers choose this part for long-life-cycle industrial controllers and avionics where the 25+ year production track record outweighs the desire for modern density. Pair with 0.1 uF VCC decoupling placed adjacent to the package and TTL-threshold inputs to preserve noise margin in 5V TTL systems.
おすすめ
ISA/VME Bus Address Decoder
In ISA, VME, and similar legacy peripheral buses, the EP1810LC-20 implements the full address-decode and bus-control state machine in a single device. The 12 dedicated inputs and 48 macrocells handle multiple chip-select windows, wait-state insertion logic, and interrupt acknowledge sequencing that previously required multiple PAL/GAL parts. The deterministic 20 ns tPD (Classic family timing model) ensures clean bus arbitration with no metastability surprises versus SRAM-based FPGAs. The 5V supply and TTL-compatible I/O make it directly interface-compatible with bus transceivers like the 74LS245 and 74LS373. Choose this part for industrial backplane designs still shipping today, especially where the design house prefers erasable/OTP logic that can be verified in-circuit.
おすすめ
Industrial State Machine Controller
The EP1810LC-20 implements complex sequential controllers for factory automation, motor control, and process equipment where deterministic timing matters more than raw density. Each macrocell's D/T/JK/SR flip-flop plus AND-OR plane allows classic state-machine design patterns with verified setup/hold times from the datasheet. The 50 MHz fMAX supports encoder feedback sampling at high motor RPM, while 5V TTL I/O interfaces directly to industrial sensors, optocouplers, and 24V-to-5V signal conditioners. Non-volatile UV-erasable storage means designs survive power loss with no boot time - critical for safety interlocks. The 0C to +70C commercial grade fits most factory-floor enclosures, and the industrial-temperature EP1810JI-35/EP1810JI-45 variants extend operation to -40C to +85C.
おすすめ
Peripheral Interface Controller
The EP1810LC-20 implements Centronics parallel-port emulators, GPIB controllers, SCSI termination logic, and other peripheral interfaces that need glue logic on both host and device sides. The 48 macrocells can encode the full parallel-port state machine plus associated handshake logic in a single device, while the deterministic tCO/tSU timing model lets the engineer guarantee data valid windows without place-and-route iterations. Classic EPLD outputs drive TTL loads directly, simplifying interfaces to 74LS-series transceivers and bus drivers. Although these interfaces are obsolete on modern PCs, they remain ubiquitous in test-and-measurement instruments, industrial printers, and embedded controllers. The Classic part's instant-on behavior (no configuration cycle) is a strong advantage versus SRAM-based FPGAs in production peripherals.
おすすめ
Pin-Compatible TTL Replacement
The EP1810LC-20 is widely used as a pin-compatible substitute for aging 74LS/74ALS/74F TTL MSI/LSI parts that have been discontinued. The 20 ns tPD matches the speed of 74LS and 74ALS families, while the integrated macrocell fabric eliminates the proliferation of discrete packages. Engineers designing replacements for end-of-life TTL boards can drop a single 68-pin PLCC onto a footprint-compatible adapter and recover decades of proven logic function. The device is reprogrammable via UV erase (windowed L variant) during development and lockable as OTP for production. This approach is common in military and aerospace sustainment programs that must keep legacy avionics and weapons systems operational.
おすすめ
Long-Life-Cycle Military/Avionics Sustaining
Military and aerospace programs (radar systems, avionics computers, communications gear) sustain EP1810LC-20 production because the part appears on legacy bills-of-material that must be supported for 20-30 years. The Classic EPLD's MIL-STD-883B screening (on GM883/GM883B variants) and hermetic package options (GM, GI suffix) make it suitable for high-reliability environments with extended temperature, vibration, and radiation tolerance requirements. The deterministic timing model simplifies DO-254 design assurance for airborne hardware, and the non-volatile EPROM storage means no boot PROM or configuration watchdog is required. Though Intel no longer manufactures new units, sustained-stock and aftermarket inventory is actively broker-traded for these programs. Engineers validate replacement parts against the original datasheet's DC/AC characteristics before installation.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1810LC-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1810LC-25 | EP1810LC-15 | EP1810LC-20T | EP1810LC-30 | EP1810LC-45 | EP1810JI-45 |
|---|---|---|---|---|---|---|---|
| Package | 68-pin PLCC | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 20 ns | 25 ns | 15 ns | 20 ns (same) | 30 ns | 45 ns | 45 ns |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 | 900 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Mid-range 20 ns speed grade balances cost and performance （vs EP1810LC-25)
- Cost-effective versus faster 15 ns speed grade （vs EP1810LC-15)
- Commercial temperature grade vs industrial-temp variants （vs EP1810JI-45)
設計ノート
The EP1810LC-20 requires a single +5V supply (4.75V to 5.25V) with multiple VCC and GND pins distributed around the PLCC-68 package (per the Classic datasheet pinout). Place at least one 0.1 uF ceramic decoupling capacitor adjacent to each VCC/GND pair, and add a bulk 10-47 uF tantalum or low-ESR electrolytic cap near the package to handle the CMOS switching current spikes. ICC is supply-current dependent on fMAX and output loading; estimate 50-100 mA typical for a fully toggling 48-macrocell design. Do not rely on the Classic family's internal power-on reset for sequencing with other logic - add external POR if needed.
The 68-pin PLCC package has 0.050 inch (1.27 mm) pitch J-leads on a square 0.985 inch body. Use a socket if the L (windowed) variant is selected for UV-erase reprogramming during development; otherwise solder directly for production. Route TTL inputs away from noisy clock traces to minimize crosstalk, and keep I/O traces short to reduce ringing on the 5V CMOS outputs. Add 33Ω kΩ series resistors on high-speed outputs if you observe undershoot/overshoot in the prototype. The exposed die (windowed variant) requires a UV-transparent label or socket window if in-circuit erasure is needed.
Common pitfalls when designing with the EP1810LC-20 include: (1) forgetting the 12 dedicated inputs are input-only and cannot be used as outputs - design your pinout accordingly; (2) assuming JTAG or ISP support - the Classic family uses Altera's proprietary programming algorithm via the dedicated programming pins, not JTAG; (3) exceeding the 50 MHz fMAX limit on registered paths - verify with the static timing model; (4) ignoring the OTP/security bit - once programmed and locked, the device cannot be re-read, so always archive the JEDEC fuse map; (5) confusing L (windowed ceramic) vs P (plastic OTP) vs GM (MIL-STD-883B) suffix variants - they have different temperature ranges and reprogrammability. The part is obsolete as of the early 2000s - always check long-term availability before committing to new designs.
コンプライアンス情報
EP1810LC-20 predates RoHS directive (2006). Original Altera production parts are typically non-RoHS; later aftermarket pulls may include RoHS date codes. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. Check Intel product compliance portal for lot-specific MDDS/CoC.
