EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
部品番号: EP1810LC-35 ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $71.16 | $71.16 |
| 10 | $68.5 | $685.00 |
| 100 | $62.4 | $6,240.00 |
| 500 | $55.8 | $27,900.00 |
| 1,000 | $49.2 | $49,200.00 |
EP1810LC-35 概要
An EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable member of the programmable logic family that sits in the broader hierarchy of PLDs > CPLDs > programmable logic > digital semiconductors. Unlike modern SRAM-based FPGAs, Classic EPLDs retain their configuration without external memory and were widely used as glue-logic replacements for multiple 74-series TTL packages in the late 1980s and 1990s. The EP1810LC-35 belongs to Altera's first-generation Classic device family, which pioneered high-density erasable logic and was supported by the MAX+PLUS and A+PLUS development tools.
Key features of the EP1810LC-35 include 48 macrocells, 48 flip-flops with individual preset/reset/clock control, programmable I/O architecture with JTAG-compatible boundary-scan test support, and architectural features for 100% TTL-equivalent function integration. Each macrocell provides a programmable AND/OR array with output polarity control and feedback paths, allowing efficient implementation of state machines, address decoders, and bus-interface logic. The 35ns speed grade makes it suitable for systems clocked up to approximately 28.6 MHz.
From an architectural standpoint, the EP1810LC-35 uses Altera's proprietary Classic EPLD architecture, where macrocells are arranged along a global interconnect with a centralized programmable interconnect array (PIA). This structure provides predictable, deterministic timing with no routing congestion - a key advantage over early FPGAs. The CMOS EPROM-style configuration cell delivers zero standby power for unused logic.
Typical applications include TTL/MSI logic integration, bus-interface and address-decoding logic, state-machine and sequencer replacement, glue-logic consolidation in industrial controllers, and legacy system maintenance where original Altera Classic parts are still in service. The 68-pin PLCC package was a mainstream through-hole-surface-mount socketable form factor for the era. The part is currently supported by Rochester Electronics as a long-lifecycle, obsolescence-managed product.
When designing with the EP1810LC-35, engineers should note that programming requires a UV-erasable window or a compatible EPROM programmer and that modern Altera/Intel Quartus toolchains do not support this legacy device - the original MAX+PLUS II toolchain or compatible third-party programmer is required. Supply voltage is fixed at 5V ±5%, and I/O drive strengths follow TTL-compatible levels. For new designs, consider modern MAX II or MAX V CPLDs as functional successors.
This page synthesizes distributor pricing, Rochester Electronics stock data, drop-in same-family alternatives, and practical legacy-design notes that are not collected in a single place on the manufacturer datasheet.
ドロップイン代替品: EP1810LC-35 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1810LC-35 （同一形状・フットプリント） — 相違点: Package, Technology, Mounting Type, Device Type, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP1810LC-30
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP1810LC-25
✅ ドロップイン✓ 在庫あり
$8.4 / 個
データシートを見る →EP1810LC-20
✅ ドロップイン✓ 在庫あり
$7.85 / 個
データシートを見る →EP1810LC-45
✅ ドロップイン✓ 在庫あり
$49.9 / 個
データシートを見る →EP1810JC-35
✅ ドロップイン✓ 在庫あり
$5.48 / 個
データシートを見る →EP1810JC-45
✅ ドロップイン✓ 在庫あり
$21.1 / 個
データシートを見る →EP1810LC-35 最大定格＆電気的特性
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP1810 |
| Macrocells | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | 28.6 MHz |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM |
| パッケージ | 68-pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount (socketable) |
| 動作温度 | 0C to +70C (commercial) |
| Configuration Method | UV-erase + EPROM programmer |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS |
EP1810LC-35 ピン構成
| ピン 1 | I/O — Macrocell I/O pin |
| ピン 2 | I/O — Macrocell I/O pin |
| ピン 3 | I/O — Macrocell I/O pin |
| ピン 4 | I/O — Macrocell I/O pin |
| ピン 5 | I/O — Macrocell I/O pin |
| ピン 6 | I/O — Macrocell I/O pin |
| ピン 7 | I/O — Macrocell I/O pin |
| ピン 8 | I/O — Macrocell I/O pin |
| ピン 9 | I/O — Macrocell I/O pin |
| ピン 10 | GND — Ground |
| ピン 11 | I/O — Macrocell I/O pin |
| ピン 12 | I/O — Macrocell I/O pin |
| ピン 13 | I/O — Macrocell I/O pin |
| ピン 14 | I/O — Macrocell I/O pin |
| ピン 15 | I/O — Macrocell I/O pin |
| ピン 16 | I/O — Macrocell I/O pin |
| ピン 17 | I/O — Macrocell I/O pin |
| ピン 18 | I/O — Macrocell I/O pin |
| ピン 19 | I/O — Macrocell I/O pin |
| ピン 20 | GND — Ground |
| ピン 21 | I/O — Macrocell I/O pin |
| ピン 22 | I/O — Macrocell I/O pin |
| ピン 23 | I/O — Macrocell I/O pin |
| ピン 24 | I/O — Macrocell I/O pin |
| ピン 25 | I/O — Macrocell I/O pin |
| ピン 26 | I/O — Macrocell I/O pin |
| ピン 27 | I/O — Macrocell I/O pin |
| ピン 28 | I/O — Macrocell I/O pin |
| ピン 29 | I/O — Macrocell I/O pin |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — Macrocell I/O pin |
| ピン 32 | I/O — Macrocell I/O pin |
| ピン 33 | I/O — Macrocell I/O pin |
| ピン 34 | I/O — Macrocell I/O pin |
| ピン 35 | I/O — Macrocell I/O pin |
| ピン 36 | I/O — Macrocell I/O pin |
| ピン 37 | I/O — Macrocell I/O pin |
| ピン 38 | I/O — Macrocell I/O pin |
| ピン 39 | I/O — Macrocell I/O pin |
| ピン 40 | GND — Ground |
| ピン 41 | I/O — Macrocell I/O pin |
| ピン 42 | I/O — Macrocell I/O pin |
| ピン 43 | I/O — Macrocell I/O pin |
| ピン 44 | I/O — Macrocell I/O pin |
| ピン 45 | I/O — Macrocell I/O pin |
| ピン 46 | I/O — Macrocell I/O pin |
| ピン 47 | I/O — Macrocell I/O pin |
| ピン 48 | I/O — Macrocell I/O pin |
| ピン 49 | I/O — Macrocell I/O pin |
| ピン 50 | GND — Ground |
| ピン 51 | I/O — Macrocell I/O pin |
| ピン 52 | I/O — Macrocell I/O pin |
| ピン 53 | I/O — Macrocell I/O pin |
| ピン 54 | I/O — Macrocell I/O pin |
| ピン 55 | I/O — Macrocell I/O pin |
| ピン 56 | I/O — Macrocell I/O pin |
| ピン 57 | I/O — Macrocell I/O pin |
| ピン 58 | I/O — Macrocell I/O pin |
| ピン 59 | I/O — Macrocell I/O pin |
| ピン 60 | GND — Ground |
| ピン 61 | VCC — +5V supply |
| ピン 62 | I/O — Macrocell I/O pin |
| ピン 63 | I/O — Macrocell I/O pin |
| ピン 64 | I/O — Macrocell I/O pin |
| ピン 65 | I/O — Macrocell I/O pin |
| ピン 66 | I/O — Macrocell I/O pin |
| ピン 67 | I/O — Macrocell I/O pin |
| ピン 68 | I/O — Macrocell I/O pin |
主な用途
EP1810LC-35 の用途: 6 件s: TTL/MSI Logic Integration (Glue Logic Replacement), Address Decoding and Bus Interface Logic, State Machine and Sequencer Replacement, Legacy Industrial Controller Maintenance, Avionics and Military Legacy Systems, Test Equipment and Instrument Front-End Logic.
TTL/MSI Logic Integration (Glue Logic Replacement)
The EP1810LC-35 is well suited to consolidating multiple 74-series TTL packages (74LS00, 74LS138, 74LS151, etc.) onto a single programmable device. With 48 macrocells delivering ~900 usable gates, the part can replace dozens of discrete SSI/MSI packages on legacy boards. Its 35ns propagation delay preserves the timing margins of the original TTL design, and the 5V CMOS EPROM technology drops quiescent power dramatically compared to bipolar TTL - critical for power-supply-thermal-constrained industrial control cabinets.
おすすめ
Address Decoding and Bus Interface Logic
In 80C186, 68k, and Z80-based embedded systems, the EP1810LC-35 functions as a dedicated address decoder and bus-interface controller. Its 48 macrocells are more than sufficient to implement full address-decoder trees, chip-select generation, wait-state insertion, and byte-swapping logic for 16-bit and 32-bit buses. The 35ns tpd fits comfortably within typical bus-access timing budgets of 8-16 MHz microprocessor systems, and the JTAG-compatible boundary-scan support simplifies board-level test.
おすすめ
State Machine and Sequencer Replacement
Each EP1810LC-35 macrocell provides a flip-flop with dedicated preset, reset, and clock controls, making the device ideal for implementing complex state machines and sequencers that previously required multiple PAL/GAL devices. Engineers can encode 16-, 24-, or 32-state FSMs plus combinational output decoding in a single EP1810LC-35, eliminating timing skew between state registers. The deterministic PIA-based interconnect guarantees consistent state-machine behavior regardless of logic placement.
おすすめ
Legacy Industrial Controller Maintenance
Many industrial controllers, CNC machines, and process-control systems shipped in the 1990s use EP1810-family EPLDs as central glue-logic devices. The EP1810LC-35 is the recommended direct replacement for these legacy systems because Rochester Electronics maintains factory-traceable, electrically-tested inventory that matches the original Altera specifications. Replacing a failed EP1810LC-35 on a 25-year-old PLC board avoids a costly full-system redesign and extends the operating life of installed equipment by another decade.
おすすめ
Avionics and Military Legacy Systems
Military and avionics platforms with field-deployed EP1810LC-35 EPLDs require long-life-cycle, factory-traceable replacements. Rochester Electronics specializes in sustaining production of mature Altera Classic parts for these applications, with full MIL-spec traceability. The EP1810LC-35's CMOS EPROM technology provides non-volatile configuration without battery backup - critical for vibration- and temperature-stressed avionics environments where SRAM-based FPGAs are not suitable.
おすすめ
Test Equipment and Instrument Front-End Logic
Bench-top test instruments (logic analyzers, protocol analyzers, and pattern generators) from the late 1980s through mid-1990s used EP1810-family EPLDs to implement timing generators, trigger sequencers, and parallel-data formatting. The EP1810LC-35's 35ns tpd and 28.6 MHz maximum clock support the timing budgets of these instruments, while the JTAG boundary-scan simplifies in-system test of the assembled boards. For repair shops, sourcing a Rochester-tested EP1810LC-35 restores instrument calibration and timing accuracy.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1810LC-35 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1810LC-30 | EP1810LC-25 | EP1810LC-20 | EP1810LC-45 | EP1810JC-35 | EP1810JC-45 |
|---|---|---|---|---|---|---|---|
| Brand | Rochester Electronics (originally Altera) | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Package | 68-pin PLCC (J-Lead) | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same |
| Speed Grade (tpd) | 35 ns | 30 ns (faster) | 25 ns (faster) | 20 ns (faster) | 45 ns (slower) | 35 ns (same) | 45 ns (slower) |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
| Maximum Frequency | 28.6 MHz | ~33 MHz | ~40 MHz | ~50 MHz | ~22 MHz | 28.6 MHz | ~22 MHz |
| Equivalent Gates | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
主な差別化要因
- Better speed grade for legacy designs requiring 28.6 MHz operation （vs EP1810LC-45)
- Slower but lower-cost option for legacy repair only （vs EP1810LC-30)
- Pinout-identical across entire EP1810 family for universal board compatibility （vs EP1810JC-35)
設計ノート
The EP1810LC-35 is NOT supported by modern Altera/Intel Quartus toolchains. Engineers must use the legacy MAX+PLUS II or A+PLUS development environment, which Altera discontinued decades ago. Programming requires a UV-erasable EPROM programmer compatible with the Classic family. For new designs, plan to use a MAX II, MAX V, or MAX 10 CPLD instead - the EP1810LC-35 should be reserved for legacy board repair and obsolescence-management scenarios only.
The EP1810LC-35 is specified for 5V ±5% operation (4.75V to 5.25V). Operating below 4.75V will cause timing-margin violations and possible logic errors; operating above 5.25V risks permanent CMOS damage. The PLCC-68 package's CMOS EPROM technology draws negligible standby current (microamps), but dynamic current at 28.6 MHz can reach 50-100 mA depending on toggle rate. Decouple VCC with at least one 0.1uF ceramic capacitor per VCC pin, placed within 5mm of the package.
For 68-pin PLCC boards carrying EP1810-family EPLDs, provide a generous ground plane on the component side and stitch the PLCC socket with multiple through-hole vias to the ground plane. The Classic EPLD's PIA-based interconnect is relatively insensitive to signal-integrity issues, but high-speed designs approaching 28.6 MHz still benefit from controlled-impedance traces for clock and JTAG signals. Use a PLCC extraction tool (not a screwdriver) when replacing the EP1810LC-35 in the field to avoid pin damage.
コンプライアンス情報
The EP1810LC-35 is a 1980s-era Classic EPLD originally manufactured by Altera and now sustained by Rochester Electronics. RoHS/REACH compliance was not tracked when the part was originally released; current Rochester-sold inventory compliance status is not stated in the verified web data and is therefore marked 'unknown'. For modern RoHS-compliant designs, choose a MAX II/MAX V CPLD instead.
