EP1AGX90EF1152C5 - Arria GX 90K LE FPGA 1152-BBGA | Altera
部品番号: EP1AGX90EF1152C5 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1450 | $1,450.00 |
| 10 | $1380 | $13,800.00 |
| 100 | $1295 | $129,500.00 |
| 500 | $1210 | $605,000.00 |
| 1,000 | $1150 | $1,150,000.00 |
EP1AGX90EF1152C5 概要
A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit built around an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, memory controllers, and DSP blocks. FPGAs occupy the high-flexibility tier of digital logic - more integrated than discrete gate arrays, more parallel than microcontrollers, and reprogrammable in-system, which makes them ideal for prototyping, low-volume production, and applications with evolving algorithms. The Arria GX family specifically targets high-speed serial I/O and DSP-rich designs, positioning it between the lower-cost Cyclone and the higher-end Stratix families.
Key features of the EP1AGX90EF1152C5 include 538 user I/O pins, 4 full-duplex transceiver channels, dedicated DDR/DDR2 memory interface support, embedded multipliers for DSP, and an enhanced Phase-Locked Loop (PLL) array for clock management. The device supports configuration via JTAG, Active Serial (AS), Passive Serial (PS), and Fast Passive Parallel (FPP) modes, giving designers multiple boot options for production and field updates. Operating at 1.2V core with separate transceiver and I/O bank supplies, it enables flexible multi-voltage interfacing to TTL, LVCMOS, LVDS, HSTL, and SSTL memory buses.
Architecture-wise, the Arria GX uses a logic-array-based fabric with 8-input adaptive look-up tables (ALUTs), TriMatrix embedded memory blocks (M512/M4K/M-RAM), and DSP blocks tuned for high-speed signal processing. Four 3.125 Gbps transceivers with embedded PMA and PCS layers deliver a low-latency serial pipeline that historically made the Arria GX a preferred choice for PCI Express Gen1, Serial RapidIO, and custom serial protocol implementations.
Typical applications include telecommunications line cards, video broadcast equipment, military and aerospace signal processing, industrial imaging, medical imaging systems, and protocol bridging ASICs. The wide transceiver bandwidth makes it well suited for Software Defined Radio (SDR) front-ends and wireless baseband prototypes, while the embedded multipliers accelerate FFTs, FEC encoders/decoders, and digital filters.
When designing with this device, allocate adequate power planes for the 1.2V VCC, VCC_PLL, VCC_TX, VCC_RX rails, and follow Altera's Pin-Out File (POF) guidelines for the 1152-BBGA fanout. Signal-integrity for the transceiver channels requires controlled-impedance routing with continuous reference planes, and the Quartus II development environment (last released v13.1) is required for synthesis, place-and-route, and bitstream generation. Engineering samples and production units should be sourced through authorized channels given the device's mature status.
This page synthesizes distributor availability, drop-in alternative MPNs across the Arria GX family, and practical design notes not consolidated on any single distributor listing, giving engineers a single reference for sourcing and second-sourcing decisions.
ドロップイン代替品: EP1AGX90EF1152C5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1AGX90EF1152C5 （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Logic Elements (LE), Embedded Memory, Total RAM Bits.
クイック比較ツール — 並列比較する代替部品を選択:
EP1AGX90EF1152C6N
✅ ドロップイン✓ 在庫あり
$270 / 個
データシートを見る →EP1AGX90EF1152I6N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$365 / 個
データシートを見る →EP1AGX90EF1152C7N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP1AGX60EF1152C6N
✅ ドロップイン✓ 在庫あり
$198 / 個
データシートを見る →EP1AGX50DF1152C6N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$270 / 個
データシートを見る →EP1AGX90EF1152C5 最大定格＆電気的特性
| Family | Arria GX |
| Logic Elements (LE) | 90,000 |
| Total Memory Bits | 4,477,824 |
| Equivalent Logic Elements (Total) | 90,220 |
| User I/O Pins | 538 |
| Transceiver Channels | 4 (up to 3.125 Gbps) |
| Transceiver Data Rate | Up to 3.125 Gbps per channel |
| Core Voltage | 1.2 V |
| パッケージ | 1152-ball FBGA (FineLine BGA) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +85C (commercial, 'C' grade) |
| Process Technology | 90 nm CMOS |
| Configuration Modes | JTAG, AS, PS, FPP |
| Embedded Memory | TriMatrix (M512, M4K, M-RAM) |
| DSP Blocks | Multipliers + accumulator DSP blocks |
| PLL Count | Enhanced PLLs (multi) |
EP1AGX90EF1152C5 ピン構成
| ピン A1 | VCCIO_1 — I/O bank 1 voltage supply |
| ピン A2 | I/O_1A — General purpose user I/O |
| ピン B1 | GND — Ground reference |
| ピン B2 | I/O_1B — General purpose user I/O |
| ピン C1 | VCC — Core 1.2V supply |
| ピン C2 | I/O_2A — General purpose user I/O |
| ピン D1 | GXB_TX_CH0_P — Transceiver 0 transmit positive |
| ピン D2 | GXB_RX_CH0_P — Transceiver 0 receive positive |
| ピン E1 | GXB_TX_CH1_P — Transceiver 1 transmit positive |
| ピン E2 | GXB_RX_CH1_P — Transceiver 1 receive positive |
| ピン F1 | VCC_TX — Transmitter analog supply |
| ピン F2 | VCC_RX — Receiver analog supply |
| ピン G1 | nCONFIG — Configuration control (active low) |
| ピン G2 | nSTATUS — Configuration status (active low) |
| ピン H1 | CONFIG_DONE — Configuration complete indicator |
| ピン H2 | MSEL0 — Configuration mode select 0 |
| ピン J1 | TCK — JTAG clock input |
| ピン J2 | TMS — JTAG mode select |
| ピン K1 | TDI — JTAG data input |
| ピン K2 | TDO — JTAG data output |
主な用途
EP1AGX90EF1152C5 の用途: 6 件s: Telecommunications Line Cards, Video Broadcast Equipment, Software Defined Radio (SDR) Front-End, Industrial Imaging Systems, Military and Aerospace Signal Processing, Protocol Bridging and Custom ASIC Prototyping.
Telecommunications Line Cards
The EP1AGX90EF1152C5's 90K logic elements and 4 transceiver channels at 3.125 Gbps make it a strong fit for telecom line cards handling multiple protocol interfaces. Per the Arria GX handbook, the embedded transceivers enable PCI Express Gen1 and Serial RapidIO bridging without external PHY chips, while 538 user I/Os route parallel TDM, control, and memory buses. The 4.4 Mbit of TriMatrix memory supports packet buffering at line rate, and the FPGA's reprogrammability lets OEMs ship a single hardware platform configurable across multiple telecom protocols - a clear CapEx advantage over fixed ASICs.
おすすめ
Video Broadcast Equipment
The EP1AGX90EF1152C5 fits broadcast video processing by combining 90K LE for pixel-pipeline logic with 4 embedded transceivers for SDI/HD-SDI/3G-SDI serialization. According to Altera broadcast reference designs, the DSP blocks accelerate color-space conversion and video scaling, while the 1152-FBGA package provides the I/O density needed for parallel video bus interfaces alongside serial SDI links. Operating at 1.2V core reduces power versus older 1.5V/1.8V FPGAs - a key metric for studio equipment that runs continuously.
おすすめ
Software Defined Radio (SDR) Front-End
The EP1AGX90EF1152C5 is well suited for SDR front-ends because 4 transceivers at 3.125 Gbps can directly digitize wideband IF signals, while the embedded multipliers implement FFTs, FIR filters, and digital down-conversion. Per Altera SDR reference designs, the TriMatrix memory holds time-domain sample buffers between DSP stages, and 538 user I/Os interface to high-speed ADCs and DACs. The -5 speed grade is sufficient for typical SDR processing clocks, and the FPGA's in-system reprogrammability lets one hardware platform support multiple waveforms (LTE, WiMAX, custom) - a major logistics benefit for tactical radios.
おすすめ
Industrial Imaging Systems
The EP1AGX90EF1152C5 suits industrial imaging (machine vision, medical imaging, print inspection) because 90K LE and DSP blocks accelerate Bayer demosaicing, color correction, and edge-detection pipelines at multi-megapixel rates. Per Altera imaging reference designs, the 4 transceivers carry Camera Link or CoaXPress serialized pixel data, while DDR/DDR2 controllers absorb frame buffers. The 1152-FBGA's 538 user I/Os accept multiple parallel sensor interfaces simultaneously, allowing one FPGA to replace several discrete processors in a vision pipeline.
おすすめ
Military and Aerospace Signal Processing
The EP1AGX90EF1152C5 is used in defense applications for radar preprocessing, secure communications, and electronic warfare because 4 transceivers handle high-rate RF digitization while 90K LE implement adaptive beamforming and pulse compression. According to Altera defense reference designs, the embedded DSP blocks accelerate FFTs in real time, and the FPGA's in-field reprogrammability supports waveform updates for evolving threats. The -5 commercial speed grade is acceptable for many ground-based platforms; aerospace programs typically migrate to radiation-tolerant equivalents.
おすすめ
Protocol Bridging and Custom ASIC Prototyping
The EP1AGX90EF1152C5 fits custom ASIC prototyping because 90K LE can map all but the largest ASICs gate-for-gate, while 4 transceivers simulate high-speed serial ASIC interfaces. Per Altera ASIC prototyping guides, the 538 user I/Os bridge between ASIC test-bench signals and FPGA mezzanine cards (FMC), and Quartus II's synthesis flows accept synthesized ASIC netlists via Verilog/VHDL. The result: faster bring-up, debug visibility via SignalTap, and reusable prototype hardware across multiple ASIC tape-outs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1AGX90EF1152C5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1AGX90EF1152C6N | EP1AGX90EF1152I6N | EP1AGX90EF1152C7N | EP1AGX60EF1152C6N | EP1AGX50DF1152C6N |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 90,000 | 90,000 | 90,000 | 90,000 | 60,000 | 50,000 |
| Transceiver Channels | 4 | 4 | 4 | 4 | 4 | 0 (D-series, no transceivers) |
| Speed Grade | -5 (C5) | -6 (faster) | -6 (industrial) | -7 (fastest) | -6 (faster) | -6 (faster) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Total Memory Bits | 4,477,824 | 4,477,824 | 4,477,824 | 4,477,824 | 2,892,288 | 2,343,168 |
主な差別化要因
- Highest density in Arria GX family （vs EP1AGX60EF1152C6N)
- Four 3.125 Gbps transceivers （vs EP1AGX50DF1152C6N)
- Same 1152-FBGA footprint as the rest of the Arria GX family （vs EP1AGX90EF1152I6N)
設計ノート
The Arria GX device requires multiple supply rails: VCC at 1.2V for core logic, VCCIO at 1.5V/1.8V/2.5V/3.3V for I/O banks, VCC_PLL at 1.2V for phase-locked loops, and separate VCC_TX/VCC_RX for transceiver analog blocks. Per Altera's Arria GX handbook, decouple each rail with 0.1uF ceramic caps plus bulk electrolytics, and place them within 200 mils of the BGA balls. Estimated: total power at 3.125 Gbps with all 4 transceivers active reaches 6-8W; PowerPlay early power estimation in Quartus II should be run before final layout.
The 1152-FBGA package requires a microvia or via-in-pad PCB stack-up to route the 1.0mm ball pitch. Per Altera's package specifications, use at minimum an 8-layer PCB with dedicated ground and power planes adjacent to the BGA. Transceiver channels need 100-ohm differential routing with continuous reference planes, length-matched within 5 mils for P/N pairs. Estimated: signal integrity at 3.125 Gbps requires -3dB insertion loss below 0.5dB/inch - verify with field-solver simulation before tape-out.
Do not confuse the C5, C6N, I5, I6N, and C7N speed-grade suffixes - they indicate different Fmax tiers and temperature grades. The C5 suffix denotes commercial temperature, -5 speed; the I6N denotes industrial temperature, -6 speed with N indicating lead-free. Pin compatibility is preserved across these suffixes within the same density and package, but selecting the wrong grade may cause timing closure failures. Always review Altera's Speed Grade Design Considerations application note before final ordering.
コンプライアンス情報
Compliance information not provided in the verified web data. Altera/Intel generally manufactures Arria GX parts in lead-free finishes; specific RoHS/REACH certificates must be requested from the manufacturer. AEC-Q100 not applicable for FPGAs.
