EP1AGX90EF1152I6N - Arria GX FPGA, 90K LE, FBGA-1152 | Intel
MPN: EP1AGX90EF1152I6N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $485 | $485.00 |
| 10 | $455 | $4,550.00 |
| 100 | $410 | $41,000.00 |
| 250 | $388 | $97,000.00 |
| 500 | $365 | $182,500.00 |
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View Datasheet →EP1AGX90EF1152I6N Maximum Ratings & Electrical Characteristics
| Family | Arria GX |
| Logic Elements (LE) | 90,000 |
| Configurable Logic Blocks (CLBs) | 90,220 |
| Logic Array Blocks (LABs) | 4,511 |
| Maximum User I/O | 538 |
| Embedded Memory | 4,510 Kbits |
| Transceiver Channels | 4 |
| Transceiver Data Rate | 1.25 to 3.125 Gbps |
| Core Voltage | 1.2 V |
| Package | FBGA-1152 (35x35 mm, 1.0 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial) |
| Lead-Free / RoHS | Yes (Lead Free) |
| Process Technology | 90 nm |
| Maximum Frequency | 640 MHz (internal) |
EP1AGX90EF1152I6N fbga-1152 (35x35 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for EP1AGX90EF1152I6N (fbga-1152 (35x35 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX90EF1152I6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX90EF1152I6N is suitable for 6 applications: PCI Express Endpoint Cards, Serial RapidIO Bridge and Switch, Video Processing and Display Controllers, Wireless Baseband DSP, Industrial Protocol Bridging and Gateways, Test and Measurement Instrumentation.
PCI Express Endpoint Cards
The EP1AGX90EF1152I6N's 4 integrated multi-gigabit transceivers operating at 1.25 to 3.125 Gbps provide a direct hardware path for PCI Express Gen1 x4 endpoints without external PHY chips. Per the Arria GX Device Handbook, the transceiver PCS includes built-in 8B/10B encoding, word alignment, and PCIe-compliant electrical idle and beacon signaling. The 90K LE capacity is more than sufficient for endpoint protocol stack, DMA engines, and application logic on the same die, while the 538 user I/O pins expose wide local buses and DDR2 memory interfaces. Designers implement PCIe hard IP via the Quartus II IP Catalog, configure the transceiver PLL to the 100 MHz PCIe reference clock, and use the integrated PMA to meet Gen1 TX/RX electrical compliance. This integration reduces BOM cost by $20-40 per board versus discrete PHY solutions and shortens design time.
Recommended
Serial RapidIO Bridge and Switch
Serial RapidIO (SRIO) requires deterministic low-latency serial links, and the EP1AGX90EF1152I6N's transceivers at 1.25, 2.5, and 3.125 Gbps cover SRIO 1x and 4x lane widths directly. The embedded 4-port SRIO IP from Altera/Intel implements the logical, transport, and physical layers with hardware-accelerated doorbell and message passing, leaving 60K+ LE available for switching fabric, DMA, and buffer management. The device's hardware CRC, ackID tracking, and retry logic meet SRIO specification Rev 2.1 error recovery requirements without software intervention. The 538 user I/O pins connect to local RapidIO endpoints, DDR2/QDRII shared memory, and host processor interfaces. For telecom backplane designs requiring four SRIO lanes with deterministic latency, this part eliminates external SERDES components.
Recommended
Video Processing and Display Controllers
The EP1AGX90EF1152I6N's combination of 538 user I/O, embedded multipliers, and 4,510 Kbits block RAM supports multi-channel SD/HD video processing pipelines at resolutions up to 1080p60. The device's LVDS channels support 7:1 serialized video interfaces such as FPD-Link and OpenLDI, while the parallel I/O bank handles BT.656, BT.1120, and RGB streams. Color space conversion, scaling, deinterlacing, and alpha blending fit comfortably in the 90K LE fabric, and M-RAM blocks provide line buffers for temporal processing. The transceiver links can output compressed video streams over SDI at 1.485 Gbps. Industrial temperature grade makes this part viable for medical imaging displays, broadcast monitors, and digital signage controllers operating in thermally uncontrolled enclosures.
Recommended
Wireless Baseband DSP
Wireless baseband designs benefit from the EP1AGX90EF1152I6N's embedded 18x18 multipliers, M4K memory blocks for coefficient storage, and 4 transceivers for CPRI or OBSAI fronthaul links at 1.2288 to 3.072 Gbps. The fabric supports turbo decoding, Viterbi decoding, FFT/iFFT, and channel estimation algorithms within the 90K LE budget. CPRI over the transceivers connects remote radio heads (RRH) to baseband units (BBU) with sub-microsecond latency. The 538 user I/O connects to digital front-end ADCs/DACs and antenna calibration buses. For pico-cell and small-cell 3G/4G base stations, this device combines DSP density and CPRI fronthaul in a single chip, eliminating separate DSP and framer ASICs. Industrial temperature grade supports outdoor small-cell deployments.
Recommended
Industrial Protocol Bridging and Gateways
Industrial automation gateways require multiple fieldbus protocols coexisting on a single platform. The EP1AGX90EF1152I6N supports PROFINET, EtherCAT, EtherNet/IP, and CAN interfaces through its high user I/O count and Nios II embedded processor cores instantiated in the fabric. The 4 transceivers handle industrial Ethernet at 1 Gbps for ring redundancy protocols like MRP and DLR, while parallel I/O banks interface to legacy RS-485, RS-232, and CAN transceivers. The 90K LE capacity fits protocol stacks, soft cores, and application logic simultaneously. Industrial temperature grade and long-term Intel supply program support (subject to LTB constraints) make this part viable for factory automation, substation controllers, and process control systems with 10-15 year lifecycle requirements.
Recommended
Test and Measurement Instrumentation
Test and measurement equipment designers leverage the EP1AGX90EF1152I6N's 4 transceivers and high I/O count for protocol analyzers, bit-error-rate testers, and logic analyzer probe heads. The transceivers capture serial traffic at 1.25 to 3.125 Gbps and feed it to deep trace memory in the 4,510 Kbits block RAM, while the 90K LE fabric implements trigger logic, pattern matching, and statistical analysis engines. The 538 user I/O accommodates wide parallel probe buses for FPGA-based logic analyzers with up to 532 channels. Industrial temperature grade and ruggedized FBGA packaging suit benchtop, portable, and production-floor ATE. The Quartus II SignalTap II embedded logic analyzer provides on-chip debug visibility without requiring dedicated test pins, reducing prototype bring-up time.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX90EF1152I6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX90EF1152I6 | EP1AGX90EF1152C6N | EP1AGX90EF1152C6 | EP1AGX90EF1152C5 | EP1AGX60EF1152I6N |
|---|---|---|---|---|---|---|
| Package | FBGA-1152 (35x35 mm) | FBGA-1152 (35x35 mm) - same | FBGA-1152 (35x35 mm) - same | FBGA-1152 (35x35 mm) - same | FBGA-1152 (35x35 mm) - same | FBGA-1152 (35x35 mm) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90,000 LE | 90,000 LE | 90,000 LE | 90,000 LE | 90,000 LE | 60,000 LE |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Speed Grade | -6 | -6 | -6 | -6 | -5 (slower) | -6 |
| Transceivers | 4 channels, 1.25-3.125 Gbps | 4 channels, 1.25-3.125 Gbps | 4 channels, 1.25-3.125 Gbps | 4 channels, 1.25-3.125 Gbps | 4 channels, 1.25-3.125 Gbps | 4 channels, 1.25-3.125 Gbps |
| Max User I/O | 538 | 538 | 538 | 538 | 538 | 538 |
| Lead-Free (RoHS) | Yes (N suffix) | No (lead-bearing) | Yes (N suffix) | No (lead-bearing) | No (lead-bearing) | Yes (N suffix) |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Pin-compatible commercial temperature variant available (vs EP1AGX90EF1152C6N)
- Pin-compatible lower-density downsize option (vs EP1AGX60EF1152I6N)
- Lead-bearing variant for legacy assembly compatibility (vs EP1AGX90EF1152I6)
- Speed grade -5 variant for less timing-critical designs (vs EP1AGX90EF1152C5)
Design Notes
The EP1AGX90EF1152I6N requires four separate supply rails: 1.2V VCCINT for core logic, 1.2V VCCPD for I/O pre-drivers, 2.5V/3.3V VCCIO for I/O banks, and a dedicated VCCPT rail for the 4 transceiver channels plus associated PLLs. Each transceiver channel draws approximately 100 mA from VCCPT at 3.125 Gbps with PRBS-31 pattern, so VCCPT must support 400-500 mA peak plus PLL current. Per the Arria GX Device Handbook, isolate VCCPT with a ferrite bead and bulk decoupling of at least 22 uF plus 0.1 uF X7R per channel pin pair. Use a separate LDO for VCCPT to minimize coupling from switching core transients into the sensitive SERDES analog supply. Estimated: at typical utilization the device can draw 3-5W core + 1.5W transceiver power.
The FBGA-1152 package at 1.0 mm pitch demands 4-layer minimum PCB stack-up with microvia-in-pad or via-on-pad technology for breakout. Route all 4 transceiver differential pairs (TX/RX) with 100 ohm differential impedance, length-matched within 150 mils per pair and 50 mils across all TX-RX pairs to meet channel compliance. Reference planes must be continuous under the transceiver channels; interruptions create impedance discontinuities that fail PCIe/SRIO compliance. The Arria GX pin connection guidelines mandate that unused transceiver inputs be tied to VCCPT through 10K resistors, not left floating. Provide a 156.25 MHz or 100 MHz reference clock to the REFCLK pins with HCSL signaling and 50 ohm termination to VCCPT/2.
Configure transceiver pre-emphasis and VOD settings per the Arria GX Transceiver User Guide for the target protocol and channel loss budget. At 3.125 Gbps over 20 inches of FR4, use 6 dB pre-emphasis to compensate for skin-effect loss above 1 GHz. Use IBIS-AMI models for channel simulation in HyperLynx or ANSYS SIwave before tape-out; pre-layout simulation typically reduces transceiver BER from 1E-12 to 1E-15 and avoids respins costing $50K+ and 8-12 weeks. Enable the transceiver's built-in PRBS generator/checker for in-system link margin validation during bring-up.
Three common Arria GX design pitfalls: (1) leaving VCCIO banks floating for unused I/O standards - each bank requires its own VCCIO rail even if unused; (2) using LVDS without enabling the on-chip LVDS serializer/deserializer - this fails timing closure; (3) not configuring MSEL pins correctly for the chosen configuration scheme (AS, AP, FPP, JTAG) - results in silent configuration failure. Per Altera Application Note AN474, always use the Quartus II Pin Planner's board-level verification tool before generating the SOF/POF programming file. Also note that JTAG chain order matters when combining the FPGA with a MAX II configuration CPLD on the same TCK/TMS/TD chain.
The FBGA-1152 package has theta-JA of approximately 8 C/W with a properly designed thermal pad and 12-layer PCB thermal via array under the exposed die pad. At 5W total dissipation, junction temperature rises 40C above ambient; at 10W it rises 80C. For industrial -40C to +100C operation, derate 20% to maintain junction below 125C under worst-case ambient + airflow conditions. Estimated: at typical utilization with 2 active transceivers at 2.5 Gbps, expect 4-6W total dissipation. Use the Altera PowerPlay Early Power Estimator spreadsheet to model per-design power before final thermal design.
Compliance Information
RoHS compliance confirmed via N suffix per Altera/Intel product documentation. AEC-Q100 not applicable - this is a high-speed FPGA, not an automotive-qualified IC; for automotive applications consult Arria V or Cyclone V Auto variants. REACH and conflict minerals compliance not explicitly stated in retrieved data - mark as unknown.
