EP1AGX90EF1152C6N - 90K LE Arria GX FPGA, 1152-FBGA | Intel / Altera
MPN: EP1AGX90EF1152C6N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $395 | $3,950.00 |
| 100 | $350 | $35,000.00 |
| 500 | $305 | $152,500.00 |
| 1,000 | $270 | $270,000.00 |
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View Datasheet →EP1AGX90EF1152C6N Maximum Ratings & Electrical Characteristics
| Family | Arria GX |
| Logic Elements | 90,000 |
| Embedded Memory (bits) | 4,477,824 |
| Logic Array Blocks (LABs) | 4,511 |
| User I/Os | 538 |
| Package | 1152-FBGA (35 mm x 35 mm) |
| Mounting Type | Surface Mount |
| Supply Voltage - Core | 1.15 V to 1.25 V |
| Operating Temperature (TJ) | 0 °C to 85 °C (commercial) |
| Speed Grade | C6 |
| Lead Free / RoHS | Yes (N finish) |
| Transceivers | 3.125 Gbps multi-gigabit transceiver channels |
| Configuration Interface | JTAG boundary-scan |
| Introduction Date | May 01, 2007 |
| Estimated EOL Date | 2023 |
EP1AGX90EF1152C6N Pin Configuration
| Pin B13 | VCC — Core supply voltage (1.15 V to 1.25 V) |
| Pin D5 | VCCAUX — Auxiliary supply for configuration and I/O |
| Pin A1 | GND — Ground reference |
| Pin AC11 | IO — General-purpose user I/O |
| Pin U31 | DIFFIO — Differential I/O pair |
| Pin F2 | TX — Transceiver transmit differential pair |
| Pin F3 | RX — Transceiver receive differential pair |
| Pin AJ4 | REFCLK — Transceiver reference clock input |
| Pin AH8 | TCK — JTAG test clock |
| Pin AG9 | TMS — JTAG test mode select |
| Pin AF10 | TDI — JTAG test data in |
| Pin AE11 | TDO — JTAG test data out |
| Pin AD12 | nCONFIG — Configuration control (active low) |
| Pin AC13 | nSTATUS — Configuration status (active low) |
| Pin AB14 | CONFIG_DONE — Configuration complete (open drain) |
| Pin Y15 | DCLK — Configuration clock |
| Pin W16 | DATA0 — Configuration data input |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX90EF1152C6N is suitable for 6 applications: Telecom Line Cards with SERDES Aggregation, Video Broadcast and Imaging Pipelines, Software-Defined Radio Baseband Preprocessing, Industrial Machine Vision Inspection, High-Speed Data Acquisition Front End, ASIC Prototyping for Mid-Range Designs.
Telecom Line Cards with SERDES Aggregation
The EP1AGX90EF1152C6N's 3.125 Gbps multi-gigabit transceivers and 538 user I/Os make it well-suited for telecom line-card aggregation. Protocol support includes PCI Express, Gigabit Ethernet, Serial RapidIO, and SerialLite II on hard IP SERDES channels, freeing fabric logic for queue management and packet processing. The 90K logic elements plus 4,477,824 bits of embedded memory handle forwarding tables and on-chip packet buffering without external SRAM. Placed on a line card with PHY and switch fabric interfaces, it provides deterministic timing closure and substantial headroom for protocol offload. Compared to a soft SERDES implementation, hard transceivers reduce logic usage and power by 40-60%, which is critical for port-dense line cards.
Recommended
Video Broadcast and Imaging Pipelines
The 90K logic elements, embedded multipliers, and DSP blocks of the EP1AGX90EF1152C6N map directly onto broadcast video pipelines that perform de-interlacing, scaling, color-space conversion, and frame-rate conversion in real time. The 538 user I/Os give designers enough pins to interface multiple SDI or HDMI receiver/transmitter PHYs without external mux logic. Embedded memory (4,477,824 bits) provides line buffers and frame-delay storage, reducing the need for external DDR. Running at the C6 speed grade, internal DSP blocks comfortably meet 1080p60 throughput budgets. Compared to a discrete DSP + FPGA split, a single Arria GX reduces BOM and PCB complexity for broadcast equipment racks.
Recommended
Software-Defined Radio Baseband Preprocessing
The hard 3.125 Gbps transceivers receive digitized IF or baseband samples from ADC front ends, while the EP1AGX90EF1152C6N's DSP blocks perform channelization, decimation, and digital down-conversion. 90K logic elements are sufficient for FFT engines, polyphase filter banks, and digital up-conversion for multi-channel SDR systems. The 1152-FBGA package supports the thermal dissipation needed for sustained baseband DSP workloads. Embedded memory holds overlap-save FFT buffers, eliminating external SRAM for medium channel counts. For multi-antenna MIMO or phased-array radio systems, this part balances logic, memory, and SERDES without paying for higher-end Stratix silicon.
Recommended
Industrial Machine Vision Inspection
Camera interfaces in industrial inspection systems use CoaXPress, Camera Link, or GigE Vision protocols that benefit from the EP1AGX90EF1152C6N's high-speed transceivers. Once image data is on-chip, 90K logic elements and dedicated multipliers run real-time defect detection, blob analysis, and edge detection pipelines. The 538 user I/Os interface to multiple cameras, lighting controllers, and reject-solenoid actuators simultaneously. Embedded memory holds multi-line image buffers for line-scan cameras. Industrial-grade temperature variant EP1AGX90EF1152I6N (-40C to +100C TJ) is often preferred for factory floor vibration and temperature swing conditions.
Recommended
High-Speed Data Acquisition Front End
Test and measurement equipment streams multi-GS/s ADC data into FPGAs for real-time triggering, decimation, and disk streaming. The EP1AGX90EF1152C6N's transceivers accept JESD204B-class ADC data lanes, and the 90K logic elements implement digital down-conversion, FIR filtering, and FFT analysis channels. The 1152-FBGA package supports enough transceiver channels for several synchronized ADC chips. Embedded memory buffers trigger pre-fill windows. Compared to a dedicated DSP ASIC, this FPGA can be reconfigured to support new ADC standards or trigger modes without hardware respin, accelerating instrument development cycles.
Recommended
ASIC Prototyping for Mid-Range Designs
ASIC design teams prototype mid-range SoCs on FPGAs to validate RTL before tape-out. The EP1AGX90EF1152C6N's 90K logic elements handle processor cores, peripheral IP, and interconnect fabrics that map onto mid-range ASICs. Embedded memory and DSP blocks preview ASIC hard-IP behavior. Multiple FPGAs can be ganged on a prototyping board via high-speed transceivers to emulate larger ASICs. Compared to ASIC tape-out, FPGA prototyping cuts debug cycles from weeks to hours. Quartus II synthesis and the 1152-FBGA package footprint are well-documented in the Arria GX development kit, simplifying lab bring-up.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX90EF1152C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX90EF1152I6N | EP1AGX60EF1152C6N | EP1AGX90EF1152C6 | EP1AGX90EF1152C5 | EP1AGX60EF1152I6N | EP1AGX50DF1152C6N |
|---|---|---|---|---|---|---|---|
| Package | 1152-FBGA (35x35) | 1152-FBGA (35x35) | 1152-FBGA (35x35) | 1152-FBGA (35x35) | 1152-FBGA (35x35) | 1152-FBGA | 1152-FBGA |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90,000 | 90,000 | 60,000 (-33%) | 90,000 | 90,000 | 60,000 | 50,000 |
| Operating Temperature | 0 °C to 85 °C (commercial) | -40 °C to +100 °C (industrial) | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | -40 °C to +100 °C | 0 °C to 85 °C |
| Speed Grade | C6 | I6 | C6 | C6 | C5 (slower) | I6 | C6 |
| Embedded Memory (bits) | 4,477,824 | 4,477,824 | [DATA_NEEDED] | 4,477,824 | 4,477,824 | [DATA_NEEDED] | [DATA_NEEDED] |
| Transceiver Data Rate | 3.125 Gbps | 3.125 Gbps | 3.125 Gbps | 3.125 Gbps | 3.125 Gbps | 3.125 Gbps | 3.125 Gbps |
| User I/Os | 538 | 538 | 538 | 538 | 538 | 538 | 538 |
| Lead-Free / RoHS | Yes | Yes | Yes | Unknown | Unknown | Yes | Yes |
Key Differentiators
- Highest logic density in the Arria GX 1152-FBGA family (vs EP1AGX60EF1152C6N)
- Commercial temperature bin with industrial pinout-compatible variant available (vs EP1AGX90EF1152I6N)
- Same package footprint with multiple speed grades for design flexibility (vs EP1AGX90EF1152C5)
Design Notes
Power estimation must be performed early using the Altera PowerPlay Early Power Estimator (EPE) before pin-out finalization for the EP1AGX90EF1152C6N. Estimated: at 50% toggle rate, 50% logic utilization, and 8 active transceivers at 3.125 Gbps, the 90K-LE Arria GX device typically draws 6-10 W from the 1.15-1.25 V core rail, plus auxiliary VCCAUX and VCCIO rails. Decoupling per the Arria GX pin connection guidelines in Quartus II is mandatory; bulk decoupling should use 22-47 uF polymer capacitors placed within 1 inch of the BGA footprint, with 0.1 uF and 0.01 uF ceramics at every VCC pin group.
The 1152-FBGA package requires a multilayer PCB with buried vias or microvia stack-ups to fan out all 538 user I/Os plus transceiver lanes. Estimated: a 12-layer stack-up with 1-oz copper outer layers and 0.5-oz inner layers is typical for production designs. Maintain 100-ohm differential impedance for transceiver TX/RX pairs (per the Arria GX pin connection guidelines) and 50-ohm single-ended for general-purpose I/O. JTAG chain pins (TCK, TMS, TDI, TDO) must be brought to a test header on every revision for boundary-scan test.
Common pitfalls when designing with the EP1AGX90EF1152C6N include: (1) forgetting the VCCPD rail for I/O pre-drivers, which causes configuration errors; (2) failing to set MSEL pins correctly for the desired configuration scheme (AS, PS, JTAG); (3) not preserving nCONFIG and nSTATUS as dedicated configuration pins; (4) routing high-speed transceiver lanes without length matching. The Arria GX datasheet specifies that TX/RX lanes within a group must be matched within 150 mil; mismatched lanes cause bit-error-rate degradation at 3.125 Gbps.
The 1152-FBGA package has a thermal resistance (theta_JA) typically around 4-6 C/W with proper PCB thermal design (estimated, with 1 square inch of inner copper pour). At full utilization the device can dissipate 8-12 W; adequate airflow (200 LFM minimum) is recommended for production deployments, with a heatsink for industrial environments where the I6N variant is used. Junction temperature must remain below 85 C for commercial grade and 100 C for industrial.
Compliance Information
RoHS compliant per N finish in MPN. Last-time-buy status per GlobalSpec listing (Estimated EOL Date 2023). Country of Origin: Republic of Korea. ECCN: 3A991.
