EP1AGX90EF1152C5 - Arria GX 90K LE FPGA 1152-BBGA | Altera
MPN: EP1AGX90EF1152C5 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1450 | $1,450.00 |
| 10 | $1380 | $13,800.00 |
| 100 | $1295 | $129,500.00 |
| 500 | $1210 | $605,000.00 |
| 1,000 | $1150 | $1,150,000.00 |
Drop-in alternatives for EP1AGX90EF1152C5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1AGX90EF1152C6N
β Drop-Inβ In Stock
$270 / Unit
View Datasheet βEP1AGX90EF1152I6N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$365 / Unit
View Datasheet βEP1AGX90EF1152C7N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1AGX60EF1152C6N
β Drop-Inβ In Stock
$198 / Unit
View Datasheet βEP1AGX50DF1152C6N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$270 / Unit
View Datasheet βEP1AGX90EF1152C5 Maximum Ratings & Electrical Characteristics
| Family | Arria GX |
| Logic Elements (LE) | 90,000 |
| Total Memory Bits | 4,477,824 |
| Equivalent Logic Elements (Total) | 90,220 |
| User I/O Pins | 538 |
| Transceiver Channels | 4 (up to 3.125 Gbps) |
| Transceiver Data Rate | Up to 3.125 Gbps per channel |
| Core Voltage | 1.2 V |
| Package | 1152-ball FBGA (FineLine BGA) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (commercial, 'C' grade) |
| Process Technology | 90 nm CMOS |
| Configuration Modes | JTAG, AS, PS, FPP |
| Embedded Memory | TriMatrix (M512, M4K, M-RAM) |
| DSP Blocks | Multipliers + accumulator DSP blocks |
| PLL Count | Enhanced PLLs (multi) |
EP1AGX90EF1152C5 Pin Configuration
| Pin A1 | VCCIO_1 β I/O bank 1 voltage supply |
| Pin A2 | I/O_1A β General purpose user I/O |
| Pin B1 | GND β Ground reference |
| Pin B2 | I/O_1B β General purpose user I/O |
| Pin C1 | VCC β Core 1.2V supply |
| Pin C2 | I/O_2A β General purpose user I/O |
| Pin D1 | GXB_TX_CH0_P β Transceiver 0 transmit positive |
| Pin D2 | GXB_RX_CH0_P β Transceiver 0 receive positive |
| Pin E1 | GXB_TX_CH1_P β Transceiver 1 transmit positive |
| Pin E2 | GXB_RX_CH1_P β Transceiver 1 receive positive |
| Pin F1 | VCC_TX β Transmitter analog supply |
| Pin F2 | VCC_RX β Receiver analog supply |
| Pin G1 | nCONFIG β Configuration control (active low) |
| Pin G2 | nSTATUS β Configuration status (active low) |
| Pin H1 | CONFIG_DONE β Configuration complete indicator |
| Pin H2 | MSEL0 β Configuration mode select 0 |
| Pin J1 | TCK β JTAG clock input |
| Pin J2 | TMS β JTAG mode select |
| Pin K1 | TDI β JTAG data input |
| Pin K2 | TDO β JTAG data output |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX90EF1152C5 is suitable for 6 applications: Telecommunications Line Cards, Video Broadcast Equipment, Software Defined Radio (SDR) Front-End, Industrial Imaging Systems, Military and Aerospace Signal Processing, Protocol Bridging and Custom ASIC Prototyping.
Telecommunications Line Cards
The EP1AGX90EF1152C5's 90K logic elements and 4 transceiver channels at 3.125 Gbps make it a strong fit for telecom line cards handling multiple protocol interfaces. Per the Arria GX handbook, the embedded transceivers enable PCI Express Gen1 and Serial RapidIO bridging without external PHY chips, while 538 user I/Os route parallel TDM, control, and memory buses. The 4.4 Mbit of TriMatrix memory supports packet buffering at line rate, and the FPGA's reprogrammability lets OEMs ship a single hardware platform configurable across multiple telecom protocols - a clear CapEx advantage over fixed ASICs.
Recommended
Video Broadcast Equipment
The EP1AGX90EF1152C5 fits broadcast video processing by combining 90K LE for pixel-pipeline logic with 4 embedded transceivers for SDI/HD-SDI/3G-SDI serialization. According to Altera broadcast reference designs, the DSP blocks accelerate color-space conversion and video scaling, while the 1152-FBGA package provides the I/O density needed for parallel video bus interfaces alongside serial SDI links. Operating at 1.2V core reduces power versus older 1.5V/1.8V FPGAs - a key metric for studio equipment that runs continuously.
Recommended
Software Defined Radio (SDR) Front-End
The EP1AGX90EF1152C5 is well suited for SDR front-ends because 4 transceivers at 3.125 Gbps can directly digitize wideband IF signals, while the embedded multipliers implement FFTs, FIR filters, and digital down-conversion. Per Altera SDR reference designs, the TriMatrix memory holds time-domain sample buffers between DSP stages, and 538 user I/Os interface to high-speed ADCs and DACs. The -5 speed grade is sufficient for typical SDR processing clocks, and the FPGA's in-system reprogrammability lets one hardware platform support multiple waveforms (LTE, WiMAX, custom) - a major logistics benefit for tactical radios.
Recommended
Industrial Imaging Systems
The EP1AGX90EF1152C5 suits industrial imaging (machine vision, medical imaging, print inspection) because 90K LE and DSP blocks accelerate Bayer demosaicing, color correction, and edge-detection pipelines at multi-megapixel rates. Per Altera imaging reference designs, the 4 transceivers carry Camera Link or CoaXPress serialized pixel data, while DDR/DDR2 controllers absorb frame buffers. The 1152-FBGA's 538 user I/Os accept multiple parallel sensor interfaces simultaneously, allowing one FPGA to replace several discrete processors in a vision pipeline.
Recommended
Military and Aerospace Signal Processing
The EP1AGX90EF1152C5 is used in defense applications for radar preprocessing, secure communications, and electronic warfare because 4 transceivers handle high-rate RF digitization while 90K LE implement adaptive beamforming and pulse compression. According to Altera defense reference designs, the embedded DSP blocks accelerate FFTs in real time, and the FPGA's in-field reprogrammability supports waveform updates for evolving threats. The -5 commercial speed grade is acceptable for many ground-based platforms; aerospace programs typically migrate to radiation-tolerant equivalents.
Recommended
Protocol Bridging and Custom ASIC Prototyping
The EP1AGX90EF1152C5 fits custom ASIC prototyping because 90K LE can map all but the largest ASICs gate-for-gate, while 4 transceivers simulate high-speed serial ASIC interfaces. Per Altera ASIC prototyping guides, the 538 user I/Os bridge between ASIC test-bench signals and FPGA mezzanine cards (FMC), and Quartus II's synthesis flows accept synthesized ASIC netlists via Verilog/VHDL. The result: faster bring-up, debug visibility via SignalTap, and reusable prototype hardware across multiple ASIC tape-outs.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX90EF1152C5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX90EF1152C6N | EP1AGX90EF1152I6N | EP1AGX90EF1152C7N | EP1AGX60EF1152C6N | EP1AGX50DF1152C6N |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same | 1152-FBGA - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 90,000 | 90,000 | 90,000 | 90,000 | 60,000 | 50,000 |
| Transceiver Channels | 4 | 4 | 4 | 4 | 4 | 0 (D-series, no transceivers) |
| User I/O | 538 | 538 | 538 | 538 | 538 | [DATA_NEEDED] |
| Speed Grade | -5 (C5) | -6 (faster) | -6 (industrial) | -7 (fastest) | -6 (faster) | -6 (faster) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Total Memory Bits | 4,477,824 | 4,477,824 | 4,477,824 | 4,477,824 | 2,892,288 | 2,343,168 |
Key Differentiators
- Highest density in Arria GX family (vs EP1AGX60EF1152C6N)
- Four 3.125 Gbps transceivers (vs EP1AGX50DF1152C6N)
- Same 1152-FBGA footprint as the rest of the Arria GX family (vs EP1AGX90EF1152I6N)
Design Notes
The Arria GX device requires multiple supply rails: VCC at 1.2V for core logic, VCCIO at 1.5V/1.8V/2.5V/3.3V for I/O banks, VCC_PLL at 1.2V for phase-locked loops, and separate VCC_TX/VCC_RX for transceiver analog blocks. Per Altera's Arria GX handbook, decouple each rail with 0.1uF ceramic caps plus bulk electrolytics, and place them within 200 mils of the BGA balls. Estimated: total power at 3.125 Gbps with all 4 transceivers active reaches 6-8W; PowerPlay early power estimation in Quartus II should be run before final layout.
The 1152-FBGA package requires a microvia or via-in-pad PCB stack-up to route the 1.0mm ball pitch. Per Altera's package specifications, use at minimum an 8-layer PCB with dedicated ground and power planes adjacent to the BGA. Transceiver channels need 100-ohm differential routing with continuous reference planes, length-matched within 5 mils for P/N pairs. Estimated: signal integrity at 3.125 Gbps requires -3dB insertion loss below 0.5dB/inch - verify with field-solver simulation before tape-out.
Do not confuse the C5, C6N, I5, I6N, and C7N speed-grade suffixes - they indicate different Fmax tiers and temperature grades. The C5 suffix denotes commercial temperature, -5 speed; the I6N denotes industrial temperature, -6 speed with N indicating lead-free. Pin compatibility is preserved across these suffixes within the same density and package, but selecting the wrong grade may cause timing closure failures. Always review Altera's Speed Grade Design Considerations application note before final ordering.
Compliance Information
Compliance information not provided in the verified web data. Altera/Intel generally manufactures Arria GX parts in lead-free finishes; specific RoHS/REACH certificates must be requested from the manufacturer. AEC-Q100 not applicable for FPGAs.
