EPC1LC20W - 1Mb Serial Config Flash, PLCC-20 | Intel / Altera
部品番号: EPC1LC20W ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $16.91 | $16.91 |
| 10 | $14.2 | $142.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.55 | $9,550.00 |
EPC1LC20W 概要
A configuration device is a non-volatile serial memory that holds the FPGA's programming bitstream and serially shifts it into the SRAM-based logic device through a dedicated configuration interface (typically a 4-wire or 8-wire passive serial / Fast Passive Parallel link). Because SRAM cells lose their configuration when power is removed, the system MUST use a configuration memory like the EPC1LC20 to restore the design on every boot. Within the broader taxonomy, the EPC1LC20 sits in the configuration memory sub-class of memory ICs, which itself belongs to programmable logic support and FPGA configuration memory hierarchies.
Key features include 1 Mbit of non-volatile storage, a serial configuration interface operating at up to 8 MHz, low-power CMOS technology with a typical standby current below 100 uA, 3.3V or 5V supply compatibility, and dedicated nSTATUS, nCONFIG, and CONF_DONE handshake pins that coordinate FPGA configuration handshaking. The 20-pin PLCC package is through-hole and socket-compatible with classic Altera development boards.
The EPC1LC20 implements a simple state machine that drives configuration pins automatically: it monitors nCONFIG, asserts nSTATUS to acknowledge FPGA readiness, and clocks out data on the FPGA's DATA0 / DCLK pins until CONF_DONE goes high. Reconfiguration (in-system programming) is triggered by toggling nCONFIG, allowing field updates without removing the FPGA from the board.
Typical applications include Altera FLEX 10K / ACEX 1K / Cyclone FPGA configuration storage, industrial control boards using MAX7000S CPLDs, retrofit and legacy board repair, and Avionics / military systems where a non-volatile FPGA boot source is mandated. The PLCC-20 socketed form factor is particularly suited to legacy through-hole designs where field replacement of the configuration memory is desirable.
When designing with this device, ensure the EPC1LC20W sits close to the FPGA with short, parallel DATA / DCLK traces to minimize skew. Decoupling of 0.1 uF and 10 uF near the VCC pin is recommended. For new designs, prefer the modern EPCQ-series (EPCQ32, EPCQ64, EPCQ128, EPCQ256) which are smaller, faster, and offered in surface-mount packages - the EPC1LC20W is primarily a legacy / legacy-replacement part.
ドロップイン代替品: EPC1LC20W — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPC1LC20W （同一形状・フットプリント） — 相違点: Memory Type, Mounting Type, Package, Compatible FPGA Families, Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPC1LC20N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.4 / 個
データシートを見る →EPC1LC20C
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.4 / 個
データシートを見る →EPC1LC20HEC
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.6 / 個
データシートを見る →EPC1LC20CEC
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.2 / 個
データシートを見る →EPC1LC20U
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.75 / 個
データシートを見る →EPC1LC20
✅ ドロップイン✓ 在庫あり
$7.95 / 個
データシートを見る →EPC1LC20W 最大定格＆電気的特性
| メモリタイプ | Serial Configuration Flash |
| Memory Density | 1 Mbit |
| インターフェース | Serial (Altera passive serial configuration) |
| 最大クロック周波数 | 8 MHz |
| 電源電圧 | 3.0 V to 5.5 V |
| パッケージ | PLCC-20 (J-lead, through-hole) |
| ピン数 | 20 |
| Configuration Handshake Pins | nCONFIG, nSTATUS, CONF_DONE |
| Reconfiguration Support | Yes (nCONFIG toggle triggers reload) |
| Compatible FPGA Families | Classic, MAX, FLEX, ACEX, Cyclone, APEX |
| 実装タイプ | Through-Hole (PLCC socket or solder) |
EPC1LC20W ピン構成
| ピン 1 | GND — Ground reference |
| ピン 2 | DATA — Serial configuration data output to FPGA |
| ピン 3 | DCLK — Configuration clock input from FPGA |
| ピン 4 | nSTATUS — Active-low status hand-shake to FPGA |
| ピン 5 | nCONFIG — Active-low configuration control from FPGA |
| ピン 6 | CONF_DONE — Active-high configuration-complete output |
| ピン 7 | VCC — Power supply (3.0 V to 5.5 V) |
| ピン 8 | NC — Not connected (per datasheet) |
| ピン 9 | NC — Not connected (per datasheet) |
| ピン 10 | NC — Not connected (per datasheet) |
| ピン 11 | NC — Not connected (per datasheet) |
| ピン 12 | OE — Output enable / nCS (chip select) |
| ピン 13 | NC — Not connected (per datasheet) |
| ピン 14 | NC — Not connected (per datasheet) |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | GND — Ground reference |
主な用途
EPC1LC20W の用途: 6 件s: Altera FLEX 10K FPGA Configuration Storage, ACEX 1K FPGA Boot Source, MAX 7000S CPLD Configuration, Industrial Control PLC Backplane, Legacy Avionics / Military Retrofit, Test & Measurement Instrumentation.
Altera FLEX 10K FPGA Configuration Storage
The EPC1LC20W is the canonical configuration memory for Altera FLEX 10K FPGAs in legacy industrial designs. FLEX 10K bitstreams up to 1 Mbit fit exactly within the EPC1LC20W's 1 Mbit density, and the passive-serial interface natively matches the FLEX 10K configuration pins (DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE). When the FLEX powers up, the EPC1LC20W automatically clocks out the stored bitstream; designers do not need a microcontroller to manage boot.
おすすめ
ACEX 1K FPGA Boot Source
Altera ACEX 1K FPGAs such as the EP1K30QI and EP1K100QC208 use the EPC1LC20W as their primary configuration memory. ACEX 1K bitstreams are typically 250 kbit to 1 Mbit, so the EPC1LC20W's 1 Mbit capacity covers most designs. The passive-serial interface is electrically identical between the two devices, allowing direct connection without glue logic - a key advantage over microcontroller-based boot schemes.
おすすめ
MAX 7000S CPLD Configuration
Although MAX 7000S CPLDs use on-chip EEPROM for configuration and do not strictly require an external boot device, the EPC1LC20W is sometimes used in multi-CPLD designs or for storing shadow bitstreams for field updates. The 8 MHz passive-serial clock easily handles the modest bitstream size of MAX CPLDs. Designers using MAX 7000S in industrial control systems historically added the EPC1LC20W as a redundancy/recovery path.
おすすめ
Industrial Control PLC Backplane
PLC and process-control backplanes built around FLEX 10K or ACEX 1K FPGAs typically place the EPC1LC20W in a PLCC socket on the CPU board so that firmware updates can be performed by swapping the configuration memory. The socketed PLCC-20 footprint is the industry-standard for this swap-friendly approach, allowing technicians to upgrade bitstream versions in the field without JTAG tools.
おすすめ
Legacy Avionics / Military Retrofit
Avionics and military systems built in the late 1990s and early 2000s rely on the EPC1LC20W for SRAM FPGA boot. The 'HEC' (Hi-rel Enhanced Ceramic) and 'CEC' (Ceramic Enhanced) variants are screened for radiation tolerance and extended temperature operation, making them suitable for flight-control retrofits. The PLCC-20 footprint supports socketed field-replacement which is critical for MRO operations.
おすすめ
Test & Measurement Instrumentation
Test equipment such as logic analyzers, oscilloscopes, and protocol analyzers from the early 2000s often used ACEX 1K or FLEX 10K FPGAs paired with the EPC1LC20W for boot. The 8 MHz passive-serial clock is fast enough to load typical test-equipment bitstreams in well under 1 second, satisfying power-on-to-ready timing requirements. The PLCC-20 socketed form factor also simplifies board rework in test environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPC1LC20W — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPC1LC20N | EPC1LC20C | EPC1LC20HEC | EPC1LC20CEC | EPC1LC20U |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Density | 1 Mbit | 1 Mbit | 1 Mbit | 1 Mbit | 1 Mbit | 1 Mbit |
| Max Clock Frequency | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| Interface | Altera Passive-Serial | Altera Passive-Serial | Altera Passive-Serial | Altera Passive-Serial | Altera Passive-Serial | Altera Passive-Serial |
| Supply Voltage | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V |
| Temperature Grade | Commercial (standard) | Commercial | Commercial | Military / Hi-rel ceramic | Military / Ceramic enhanced | Commercial |
| Lifecycle Status | Obsolete | Obsolete (stock only) | Obsolete (stock only) | Obsolete (hi-rel stock only) | Obsolete (hi-rel stock only) | Obsolete (stock only) |
| Unit Price (qty 1, USD) | $16.91 | $14-16 (estimated stock) | $15-18 (estimated stock) | $40-80 (estimated hi-rel stock) | $50-90 (estimated hi-rel stock) | $14-16 (estimated stock) |
主な差別化要因
- Socketed PLCC-20 form factor enables field-swap upgrades （vs EPCQ32 (SOIC-8))
- Hi-rel ceramic-screened variants available for avionics （vs EPC1LC20N (commercial-only))
- Native passive-serial interface - no microcontroller required （vs Microcontroller + SPI flash boot scheme)
設計ノート
The EPC1LC20W only supports Altera passive-serial configuration mode. Designers migrating from FLEX/ACEX/Classic to Cyclone III/IV/V/10 must NOT use the EPC1LC20W - those FPGA families require larger Active Serial (AS) configuration memories such as EPCS16, EPCS64, EPCQ32, or EPCQ64 with a 4-wire SPI-like AS interface. Mixing passive-serial and active-serial pinout assumptions will lock the board from booting.
Place the EPC1LC20W within 50 mm of the FPGA's configuration pins to minimize DCLK/DATA trace skew. Use matched-length routing (within 5 mm) for DCLK and DATA0 and route both signals over a continuous ground plane. Add 0.1 uF and 10 uF decoupling capacitors on the VCC pin (PLCC-20 pin 12) within 3 mm of the package body.
nCONFIG, nSTATUS, and CONF_DONE are open-drain handshake pins that require external 10 kohm pull-up resistors to VCC. Without these pull-ups the FPGA cannot reliably complete configuration handshaking. Connect nCONFIG to a push-button or supervisor circuit if in-system reconfiguration is desired; otherwise tie nCONFIG high through the 10 kohm pull-up.
Although the EPC1LC20W accepts 3.0-5.5 V, the FPGA's VCCIO supply for the configuration bank may be different (e.g., 2.5 V on Cyclone). When powering the EPC1LC20W at 3.3 V and the FPGA configuration bank at 2.5 V, a level-shifter or series resistor is required on DCLK/DATA to avoid damage. For pure FLEX 10K / ACEX 1K designs at 5 V, no level-shifting is needed.
コンプライアンス情報
RoHS / lead-free status could not be verified from the provided data. As a legacy Altera part from the early 2000s, the original EPC1LC20W was likely SnPb-finished; HEC/CEC ceramic variants were typically NOT RoHS-compliant. Buyers requiring RoHS parts should request documentation from the independent distributor before placing orders.
