EPM7128SQC160-10N - 128-Macrocell MAX 7000 CPLD, 100MHz | Intel
MPN: EPM7128SQC160-10N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.2 | $9,200.00 |
Drop-in alternatives for EPM7128SQC160-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC160-10
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM7128SQC160-10YY
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC160-10ES
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC160-10F
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQI160-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC160-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 100 |
| Logic Elements | 160 LE (per datasheet macrocell blocks) |
| Supply Voltage (VCCINT) | 5 V |
| Operating Frequency (Counter) | 100 MHz |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Counter Frequency (fCNT) | 175.4 MHz |
| Programming Technology | EEPROM (non-volatile) |
| JTAG Support | Yes (IEEE 1149.1 BST) |
| In-System Programmable | Yes |
| Package | 160-pin PQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial, N suffix) |
| Speed Grade | -10 (10 ns pin-to-pin) |
EPM7128SQC160-10N Pin Configuration
| Pin 1 | INPUT/GCLK1 β Global clock 1 / dedicated input |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O (bank 1) |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | I/O β User I/O (bank 1) |
| Pin 14 | I/O β User I/O (bank 1) |
| Pin 15 | I/O β User I/O (bank 1) |
| Pin 16 | I/O β User I/O (bank 1) |
| Pin 17 | I/O β User I/O (bank 1) |
| Pin 18 | I/O β User I/O (bank 1) |
| Pin 19 | I/O β User I/O (bank 1) |
| Pin 20 | I/O β User I/O (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (bank 2) |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | I/O β User I/O (bank 2) |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | I/O β User I/O (bank 2) |
| Pin 28 | I/O β User I/O (bank 2) |
| Pin 29 | I/O β User I/O (bank 2) |
| Pin 30 | I/O β User I/O (bank 2) |
| Pin 31 | I/O β User I/O (bank 2) |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β User I/O (bank 2) |
| Pin 34 | I/O β User I/O (bank 2) |
| Pin 35 | I/O β User I/O (bank 2) |
| Pin 36 | I/O β User I/O (bank 2) |
| Pin 37 | I/O β User I/O (bank 2) |
| Pin 38 | I/O β User I/O (bank 2) |
| Pin 39 | I/O β User I/O (bank 2) |
| Pin 40 | I/O β User I/O (bank 2) |
| Pin 41 | I/O β User I/O (bank 2) |
| Pin 42 | I/O β User I/O (bank 2) |
| Pin 43 | I/O β User I/O (bank 2) |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β User I/O (bank 3) |
| Pin 46 | I/O β User I/O (bank 3) |
| Pin 47 | I/O β User I/O (bank 3) |
| Pin 48 | I/O β User I/O (bank 3) |
| Pin 49 | I/O β User I/O (bank 3) |
| Pin 50 | I/O β User I/O (bank 3) |
| Pin 51 | I/O β User I/O (bank 3) |
| Pin 52 | I/O β User I/O (bank 3) |
| Pin 53 | I/O β User I/O (bank 3) |
| Pin 54 | I/O β User I/O (bank 3) |
| Pin 55 | I/O β User I/O (bank 3) |
| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O (bank 3) |
| Pin 58 | I/O β User I/O (bank 3) |
| Pin 59 | I/O β User I/O (bank 3) |
| Pin 60 | I/O β User I/O (bank 3) |
| Pin 61 | I/O β User I/O (bank 3) |
| Pin 62 | I/O β User I/O (bank 3) |
| Pin 63 | I/O β User I/O (bank 3) |
| Pin 64 | I/O β User I/O (bank 3) |
| Pin 65 | I/O β User I/O (bank 3) |
| Pin 66 | I/O β User I/O (bank 3) |
| Pin 67 | I/O β User I/O (bank 3) |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O (bank 4) |
| Pin 70 | I/O β User I/O (bank 4) |
| Pin 71 | I/O β User I/O (bank 4) |
| Pin 72 | I/O β User I/O (bank 4) |
| Pin 73 | I/O β User I/O (bank 4) |
| Pin 74 | I/O β User I/O (bank 4) |
| Pin 75 | I/O β User I/O (bank 4) |
| Pin 76 | I/O β User I/O (bank 4) |
| Pin 77 | I/O β User I/O (bank 4) |
| Pin 78 | I/O β User I/O (bank 4) |
| Pin 79 | I/O β User I/O (bank 4) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O (bank 4) |
| Pin 82 | I/O β User I/O (bank 4) |
| Pin 83 | I/O β User I/O (bank 4) |
| Pin 84 | I/O β User I/O (bank 4) |
| Pin 85 | I/O β User I/O (bank 4) |
| Pin 86 | I/O β User I/O (bank 4) |
| Pin 87 | I/O β User I/O (bank 4) |
| Pin 88 | I/O β User I/O (bank 4) |
| Pin 89 | I/O β User I/O (bank 4) |
| Pin 90 | I/O β User I/O (bank 4) |
| Pin 91 | I/O β User I/O (bank 4) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O (bank 4) |
| Pin 94 | I/O β User I/O (bank 4) |
| Pin 95 | I/O β User I/O (bank 4) |
| Pin 96 | I/O β User I/O (bank 4) |
| Pin 97 | I/O β User I/O (bank 4) |
| Pin 98 | I/O β User I/O (bank 4) |
| Pin 99 | I/O β User I/O (bank 4) |
| Pin 100 | I/O β User I/O (bank 4) |
| Pin 101 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 102 | TDI β JTAG Test Data In |
| Pin 103 | TMS β JTAG Test Mode Select |
| Pin 104 | VCC β 5V supply |
| Pin 105 | GND β Ground |
| Pin 106 | TDO β JTAG Test Data Out |
| Pin 107 | I/O β User I/O (bank 1) |
| Pin 108 | I/O β User I/O (bank 1) |
| Pin 109 | I/O β User I/O (bank 1) |
| Pin 110 | I/O β User I/O (bank 1) |
| Pin 111 | I/O β User I/O (bank 1) |
| Pin 112 | I/O β User I/O (bank 1) |
| Pin 113 | I/O β User I/O (bank 1) |
| Pin 114 | I/O β User I/O (bank 1) |
| Pin 115 | I/O β User I/O (bank 1) |
| Pin 116 | I/O β User I/O (bank 1) |
| Pin 117 | I/O β User I/O (bank 1) |
| Pin 118 | VCC β 5V supply |
| Pin 119 | GND β Ground |
| Pin 120 | OE1 β Global Output Enable 1 |
| Pin 121 | OE2/GCLK2 β Global Output Enable 2 / Global Clock 2 |
| Pin 122 | INPUT/GCLRn β Dedicated input / Global Clear |
| Pin 123 | INPUT/OE2n β Dedicated input / Global OE2 |
| Pin 124 | I/O β User I/O (bank 1) |
| Pin 125 | I/O β User I/O (bank 1) |
| Pin 126 | I/O β User I/O (bank 1) |
| Pin 127 | I/O β User I/O (bank 1) |
| Pin 128 | I/O β User I/O (bank 1) |
| Pin 129 | I/O β User I/O (bank 1) |
| Pin 130 | I/O β User I/O (bank 1) |
| Pin 131 | I/O β User I/O (bank 1) |
| Pin 132 | I/O β User I/O (bank 1) |
| Pin 133 | I/O β User I/O (bank 1) |
| Pin 134 | I/O β User I/O (bank 1) |
| Pin 135 | I/O β User I/O (bank 1) |
| Pin 136 | GND β Ground |
| Pin 137 | I/O β User I/O (bank 1) |
| Pin 138 | I/O β User I/O (bank 1) |
| Pin 139 | I/O β User I/O (bank 1) |
| Pin 140 | I/O β User I/O (bank 1) |
| Pin 141 | I/O β User I/O (bank 1) |
| Pin 142 | I/O β User I/O (bank 1) |
| Pin 143 | I/O β User I/O (bank 1) |
| Pin 144 | I/O β User I/O (bank 1) |
| Pin 145 | I/O β User I/O (bank 1) |
| Pin 146 | I/O β User I/O (bank 1) |
| Pin 147 | I/O β User I/O (bank 1) |
| Pin 148 | VCC β 5V supply |
| Pin 149 | GND β Ground |
| Pin 150 | I/O β User I/O (bank 2) |
| Pin 151 | I/O β User I/O (bank 2) |
| Pin 152 | I/O β User I/O (bank 2) |
| Pin 153 | I/O β User I/O (bank 2) |
| Pin 154 | I/O β User I/O (bank 2) |
| Pin 155 | I/O β User I/O (bank 2) |
| Pin 156 | I/O β User I/O (bank 2) |
| Pin 157 | I/O β User I/O (bank 2) |
| Pin 158 | I/O β User I/O (bank 2) |
| Pin 159 | I/O β User I/O (bank 2) |
| Pin 160 | I/O β User I/O (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC160-10N is suitable for 6 applications: ISA/PCI Bus Address Decoding, Glue Logic for Microprocessor Systems, State Machine Control, Industrial Control & 5V System Prototyping, Legacy System Upgrades & Drop-In Modernization, Telecom Backplane Glue Logic.
ISA/PCI Bus Address Decoding
The EPM7128SQC160-10N is widely used for ISA and PCI bus address decoding in 5V legacy motherboards and add-in cards. Its 128 macrocells are sufficient to decode 16-bit or 32-bit address ranges with multiple chip-select outputs, while the 100 MHz counter frequency and 10 ns tPD satisfy ISA bus timing with comfortable margin. Unlike SRAM-based FPGAs, the EEPROM-backed MAX 7000 fabric boots in microseconds with no external configuration PROM, which is critical for ISA cards where BIOS enumeration must complete before the bus controller releases RESET.
Recommended
Glue Logic for Microprocessor Systems
The EPM7128SQC160-10N excels as glue logic between microprocessors, memory, and peripherals. With 128 macrocells, designers can implement wait-state generators, interrupt arbiters, and chip-select decoding in a single 5V device. The 100 user I/Os comfortably handle 32-bit data buses plus control signals, and the deterministic 10 ns pin-to-pin delay ensures no metastability surprises. Compared to discrete 74-series TTL, the MAX 7000 reduces board area by 50-70% while remaining 5V-tolerant for direct connection to legacy microprocessors.
Recommended
State Machine Control
The EPM7128SQC160-10N is ideal for implementing complex Moore/Mealy state machines in industrial controllers. Each macrocell contains a programmable flip-flop, allowing 128 independent state registers, while the global interconnect matrix (PIA) routes control signals with deterministic 10 ns delays. The 175.4 MHz counter frequency supports high-speed sequencing, and the non-volatile EEPROM fabric means state machines power up in a known condition - critical for safety interlocks where an SRAM-based FPGA might initialize unpredictably.
Recommended
Industrial Control & 5V System Prototyping
The EPM7128SQC160-10N is widely used in industrial controllers and 5V system prototyping where its -40C to +85C industrial temperature range and 5V tolerance are mandatory. It handles timing-critical functions such as PWM generation, quadrature decoding, and serial-protocol bridging (RS-232/485) without needing level shifters. Designers can iterate logic via JTAG without removing the chip from the board, and the 10 ns pin-to-pin delay provides margin for cable-driver skew compensation.
Recommended
Legacy System Upgrades & Drop-In Modernization
The EPM7128SQC160-10N serves as a drop-in modernization path for end-of-life 5V discrete logic boards. Designers can replace dozens of 74LS/74FTTL packages with one MAX 7000 part while retaining the 5V interface to upstream microprocessors. The 160-pin PQFP footprint is compatible with existing PCB layouts, and the JTAG programming chain allows rapid firmware updates without hardware rework - particularly valuable in aerospace and military retrofit programs.
Recommended
Telecom Backplane Glue Logic
The EPM7128SQC160-10N is deployed in telecom backplanes for clock distribution, bus arbitration, and protocol bridging between legacy TDM buses and newer packet fabrics. Its 100 user I/Os comfortably handle 32-bit parallel buses plus JTAG and global clock/clear signals, while 128 macrocells implement multi-channel state machines in a single device. The non-volatile EEPROM fabric is especially valuable in central-office environments where power-cycles must result in deterministic, instant-on behavior.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC160-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC160-10 | EPM7128SQC160-10YY | EPM7128SQC160-10ES | EPM7128SQC160-10F | EPM7128SQI160-10N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 100 | 100 | 100 | 100 | 100 | 100 |
| Pin-to-Pin Delay | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Counter Frequency | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial, lead-free) | -40C to +85C (engineering sample) | -40C to +85C (industrial, lead-free) | -40C to +85C (industrial) |
| RoHS Compliant | No (legacy SnPb) | No (legacy SnPb) | Yes (lead-free) | No (engineering sample) | Yes (lead-free) | No (legacy SnPb) |
Key Differentiators
- Industrial temperature grade at the standard 10 ns speed (vs EPM7128SQC160-10)
- Non-volatile EEPROM fabric - instant deterministic boot (vs EPM7128AEFC100-10 (MAX 7000A))
- Higher logic density (128 macrocells) in the same MAX 7000 family (vs EPM7128SLC84-10)
Design Notes
Estimated: at 100 MHz toggle on 32 outputs at 5V, ICC is approximately 200 mA typical and can rise to 400 mA worst-case during simultaneous switching. Place 0.1 uF + 10 uF decoupling caps adjacent to each of the four VCC pins (104, 118, 148, plus pad 1) and four GND pins (10, 21, 32, plus pad 44) to keep the global interconnect matrix quiet. The MAX 7000 is a 5V-only family - do not apply 3.3V signals directly to user I/O; use external level shifters if interfacing to modern 3.3V logic.
Route JTAG signals (TCK/TDI/TMS/TDO) in a single daisy-chain with 10K pull-ups on TCK, TDI, TMS for proper boundary-scan operation per IEEE 1149.1. Place the EPM7128SQC160-10N away from switching power converters; the PQFP-160 lead pitch is 0.5 mm, so keep high-speed traces on inner layers with a continuous ground plane on layer 2 for controlled impedance and EMI suppression.
Do not confuse the EPM7128SQC160-10N (160-pin PQFP) with the EPM7128SQC100-10N (100-pin PQFP) or the EPM7128SLC84-10 (84-pin PLCC) - these are NOT pin-compatible despite the similar prefix. When migrating from older EPM7032/EPM7064 designs, re-validate the JTAG chain order because the -10N has a different boundary-scan ID than the smaller MAX 7000 variants. For new designs in 2026, prefer the MAX II EPM570 for 3.3V core voltages.
Compliance Information
EPM7128SQC160-10N is the legacy SnPb (non-lead-free) variant. Choose EPM7128SQC160-10F or EPM7128SQC160-10YY for RoHS-compliant designs. AEC-Q100 is not applicable (CPLD is not an automotive-qualified part); MAX 7000 family is not formally AEC-Q100 qualified. No REACH/CFMI statements in retrieved data.
