EPM7128SQC160-10N - 128-Macrocell MAX 7000 CPLD, 100MHz | Intel
N.º da peça: EPM7128SQC160-10N ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $13.2 | $132,00 |
| 100 | $11.85 | $1.185,00 |
| 500 | $10.4 | $5.200,00 |
| 1.000 | $9.2 | $9.200,00 |
EPM7128SQC160-10N Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-based programmable logic device that combines the deterministic timing of PAL/GAL architectures with higher logic density. It sits hierarchically below an FPGA but above simple PLDs in the programmable logic taxonomy: CPLD -> PLD -> programmable logic -> semiconductor. Compared to FPGAs, CPLDs offer instant-on configuration, predictable timing, and lower power for moderate-density glue logic.
Key features include 128 macrocells (each with 36 product terms), 5V core supply, in-system programmability via JTAG (IEEE 1149.1), and built-in JTAG boundary-scan test circuitry on MAX 7000S devices with 128 or more macrocells. The 5-ns pin-to-pin logic delays and 175.4-MHz counter frequencies make the EPM7128SQC160-10N a strong fit for bus-interface bridging and address decoding in legacy 5V systems.
The MAX 7000 architecture employs a second-generation MAX fabric with a global interconnect matrix, programmable interconnect array (PIA), and per-macrocell flip-flops. CMOS EEPROM technology stores configuration non-volatilely, so the device powers up in a known state with no external boot PROM, a defining advantage over SRAM-based FPGAs in deterministic boot applications.
Typical applications include PCI/ISA bus interface logic, address decoding, glue logic for microprocessors, state-machine control, and 5V system prototyping. It is also used in industrial controllers, telecom backplane glue logic, and legacy system upgrades where 5V tolerance is mandatory.
When designing, note that this part is in the MAX 7000 family and shares the classic Altera ByteBlaster/USB-Blaster programming flow via JTAG. Decoupling: place 0.1 uF and 10 uF caps near each supply pin pair to keep the global interconnect matrix quiet during simultaneous switching.
This page synthesizes distributor pricing, same-family MAX 7000 drop-in alternatives (including speed-grade and temperature-grade variants), and practical design notes not found in the original manufacturer datasheet.
Alternativas drop-in para EPM7128SQC160-10N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM7128SQC160-10N (mesmo formato e footprint) — diferindo em Package, Usable Gates, Operating Temperature, Supply Voltage (VCCINT), Logic Array Blocks (LABs).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM7128SQC160-10
✅ Drop-In✓ Em estoque
$14.2 / unidade
Ver ficha técnica →EPM7128SQC160-10YY
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128SQC160-10ES
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128SQC160-10F
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128SQI160-10N
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EPM7128SQC160-10N Classificações máximas e características elétricas
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 100 |
| Logic Elements | 160 LE (per datasheet macrocell blocks) |
| Supply Voltage (VCCINT) | 5 V |
| Operating Frequency (Counter) | 100 MHz |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Counter Frequency (fCNT) | 175.4 MHz |
| Programming Technology | EEPROM (non-volatile) |
| JTAG Support | Yes (IEEE 1149.1 BST) |
| In-System Programmable | Yes |
| Encapsulamento | 160-pin PQFP |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40C to +85C (industrial, N suffix) |
| Speed Grade | -10 (10 ns pin-to-pin) |
Configuração de pinos do EPM7128SQC160-10N
| Pino 1 | INPUT/GCLK1 — Global clock 1 / dedicated input |
| Pino 2 | I/O — User I/O (bank 1) |
| Pino 3 | I/O — User I/O (bank 1) |
| Pino 4 | I/O — User I/O (bank 1) |
| Pino 5 | I/O — User I/O (bank 1) |
| Pino 6 | I/O — User I/O (bank 1) |
| Pino 7 | I/O — User I/O (bank 1) |
| Pino 8 | I/O — User I/O (bank 1) |
| Pino 9 | I/O — User I/O (bank 1) |
| Pino 10 | GND — Ground |
| Pino 11 | I/O — User I/O (bank 1) |
| Pino 12 | I/O — User I/O (bank 1) |
| Pino 13 | I/O — User I/O (bank 1) |
| Pino 14 | I/O — User I/O (bank 1) |
| Pino 15 | I/O — User I/O (bank 1) |
| Pino 16 | I/O — User I/O (bank 1) |
| Pino 17 | I/O — User I/O (bank 1) |
| Pino 18 | I/O — User I/O (bank 1) |
| Pino 19 | I/O — User I/O (bank 1) |
| Pino 20 | I/O — User I/O (bank 1) |
| Pino 21 | GND — Ground |
| Pino 22 | I/O — User I/O (bank 2) |
| Pino 23 | I/O — User I/O (bank 2) |
| Pino 24 | I/O — User I/O (bank 2) |
| Pino 25 | I/O — User I/O (bank 2) |
| Pino 26 | I/O — User I/O (bank 2) |
| Pino 27 | I/O — User I/O (bank 2) |
| Pino 28 | I/O — User I/O (bank 2) |
| Pino 29 | I/O — User I/O (bank 2) |
| Pino 30 | I/O — User I/O (bank 2) |
| Pino 31 | I/O — User I/O (bank 2) |
| Pino 32 | GND — Ground |
| Pino 33 | I/O — User I/O (bank 2) |
| Pino 34 | I/O — User I/O (bank 2) |
| Pino 35 | I/O — User I/O (bank 2) |
| Pino 36 | I/O — User I/O (bank 2) |
| Pino 37 | I/O — User I/O (bank 2) |
| Pino 38 | I/O — User I/O (bank 2) |
| Pino 39 | I/O — User I/O (bank 2) |
| Pino 40 | I/O — User I/O (bank 2) |
| Pino 41 | I/O — User I/O (bank 2) |
| Pino 42 | I/O — User I/O (bank 2) |
| Pino 43 | I/O — User I/O (bank 2) |
| Pino 44 | GND — Ground |
| Pino 45 | I/O — User I/O (bank 3) |
| Pino 46 | I/O — User I/O (bank 3) |
| Pino 47 | I/O — User I/O (bank 3) |
| Pino 48 | I/O — User I/O (bank 3) |
| Pino 49 | I/O — User I/O (bank 3) |
| Pino 50 | I/O — User I/O (bank 3) |
| Pino 51 | I/O — User I/O (bank 3) |
| Pino 52 | I/O — User I/O (bank 3) |
| Pino 53 | I/O — User I/O (bank 3) |
| Pino 54 | I/O — User I/O (bank 3) |
| Pino 55 | I/O — User I/O (bank 3) |
| Pino 56 | GND — Ground |
| Pino 57 | I/O — User I/O (bank 3) |
| Pino 58 | I/O — User I/O (bank 3) |
| Pino 59 | I/O — User I/O (bank 3) |
| Pino 60 | I/O — User I/O (bank 3) |
| Pino 61 | I/O — User I/O (bank 3) |
| Pino 62 | I/O — User I/O (bank 3) |
| Pino 63 | I/O — User I/O (bank 3) |
| Pino 64 | I/O — User I/O (bank 3) |
| Pino 65 | I/O — User I/O (bank 3) |
| Pino 66 | I/O — User I/O (bank 3) |
| Pino 67 | I/O — User I/O (bank 3) |
| Pino 68 | GND — Ground |
| Pino 69 | I/O — User I/O (bank 4) |
| Pino 70 | I/O — User I/O (bank 4) |
| Pino 71 | I/O — User I/O (bank 4) |
| Pino 72 | I/O — User I/O (bank 4) |
| Pino 73 | I/O — User I/O (bank 4) |
| Pino 74 | I/O — User I/O (bank 4) |
| Pino 75 | I/O — User I/O (bank 4) |
| Pino 76 | I/O — User I/O (bank 4) |
| Pino 77 | I/O — User I/O (bank 4) |
| Pino 78 | I/O — User I/O (bank 4) |
| Pino 79 | I/O — User I/O (bank 4) |
| Pino 80 | GND — Ground |
| Pino 81 | I/O — User I/O (bank 4) |
| Pino 82 | I/O — User I/O (bank 4) |
| Pino 83 | I/O — User I/O (bank 4) |
| Pino 84 | I/O — User I/O (bank 4) |
| Pino 85 | I/O — User I/O (bank 4) |
| Pino 86 | I/O — User I/O (bank 4) |
| Pino 87 | I/O — User I/O (bank 4) |
| Pino 88 | I/O — User I/O (bank 4) |
| Pino 89 | I/O — User I/O (bank 4) |
| Pino 90 | I/O — User I/O (bank 4) |
| Pino 91 | I/O — User I/O (bank 4) |
| Pino 92 | GND — Ground |
| Pino 93 | I/O — User I/O (bank 4) |
| Pino 94 | I/O — User I/O (bank 4) |
| Pino 95 | I/O — User I/O (bank 4) |
| Pino 96 | I/O — User I/O (bank 4) |
| Pino 97 | I/O — User I/O (bank 4) |
| Pino 98 | I/O — User I/O (bank 4) |
| Pino 99 | I/O — User I/O (bank 4) |
| Pino 100 | I/O — User I/O (bank 4) |
| Pino 101 | TCK — JTAG Test Clock (IEEE 1149.1) |
| Pino 102 | TDI — JTAG Test Data In |
| Pino 103 | TMS — JTAG Test Mode Select |
| Pino 104 | VCC — 5V supply |
| Pino 105 | GND — Ground |
| Pino 106 | TDO — JTAG Test Data Out |
| Pino 107 | I/O — User I/O (bank 1) |
| Pino 108 | I/O — User I/O (bank 1) |
| Pino 109 | I/O — User I/O (bank 1) |
| Pino 110 | I/O — User I/O (bank 1) |
| Pino 111 | I/O — User I/O (bank 1) |
| Pino 112 | I/O — User I/O (bank 1) |
| Pino 113 | I/O — User I/O (bank 1) |
| Pino 114 | I/O — User I/O (bank 1) |
| Pino 115 | I/O — User I/O (bank 1) |
| Pino 116 | I/O — User I/O (bank 1) |
| Pino 117 | I/O — User I/O (bank 1) |
| Pino 118 | VCC — 5V supply |
| Pino 119 | GND — Ground |
| Pino 120 | OE1 — Global Output Enable 1 |
| Pino 121 | OE2/GCLK2 — Global Output Enable 2 / Global Clock 2 |
| Pino 122 | INPUT/GCLRn — Dedicated input / Global Clear |
| Pino 123 | INPUT/OE2n — Dedicated input / Global OE2 |
| Pino 124 | I/O — User I/O (bank 1) |
| Pino 125 | I/O — User I/O (bank 1) |
| Pino 126 | I/O — User I/O (bank 1) |
| Pino 127 | I/O — User I/O (bank 1) |
| Pino 128 | I/O — User I/O (bank 1) |
| Pino 129 | I/O — User I/O (bank 1) |
| Pino 130 | I/O — User I/O (bank 1) |
| Pino 131 | I/O — User I/O (bank 1) |
| Pino 132 | I/O — User I/O (bank 1) |
| Pino 133 | I/O — User I/O (bank 1) |
| Pino 134 | I/O — User I/O (bank 1) |
| Pino 135 | I/O — User I/O (bank 1) |
| Pino 136 | GND — Ground |
| Pino 137 | I/O — User I/O (bank 1) |
| Pino 138 | I/O — User I/O (bank 1) |
| Pino 139 | I/O — User I/O (bank 1) |
| Pino 140 | I/O — User I/O (bank 1) |
| Pino 141 | I/O — User I/O (bank 1) |
| Pino 142 | I/O — User I/O (bank 1) |
| Pino 143 | I/O — User I/O (bank 1) |
| Pino 144 | I/O — User I/O (bank 1) |
| Pino 145 | I/O — User I/O (bank 1) |
| Pino 146 | I/O — User I/O (bank 1) |
| Pino 147 | I/O — User I/O (bank 1) |
| Pino 148 | VCC — 5V supply |
| Pino 149 | GND — Ground |
| Pino 150 | I/O — User I/O (bank 2) |
| Pino 151 | I/O — User I/O (bank 2) |
| Pino 152 | I/O — User I/O (bank 2) |
| Pino 153 | I/O — User I/O (bank 2) |
| Pino 154 | I/O — User I/O (bank 2) |
| Pino 155 | I/O — User I/O (bank 2) |
| Pino 156 | I/O — User I/O (bank 2) |
| Pino 157 | I/O — User I/O (bank 2) |
| Pino 158 | I/O — User I/O (bank 2) |
| Pino 159 | I/O — User I/O (bank 2) |
| Pino 160 | I/O — User I/O (bank 2) |
Aplicações típicas
EPM7128SQC160-10N é adequado para 6 aplicaçãos: ISA/PCI Bus Address Decoding, Glue Logic for Microprocessor Systems, State Machine Control, Industrial Control & 5V System Prototyping, Legacy System Upgrades & Drop-In Modernization, Telecom Backplane Glue Logic.
ISA/PCI Bus Address Decoding
The EPM7128SQC160-10N is widely used for ISA and PCI bus address decoding in 5V legacy motherboards and add-in cards. Its 128 macrocells are sufficient to decode 16-bit or 32-bit address ranges with multiple chip-select outputs, while the 100 MHz counter frequency and 10 ns tPD satisfy ISA bus timing with comfortable margin. Unlike SRAM-based FPGAs, the EEPROM-backed MAX 7000 fabric boots in microseconds with no external configuration PROM, which is critical for ISA cards where BIOS enumeration must complete before the bus controller releases RESET.
Recomendado
Glue Logic for Microprocessor Systems
The EPM7128SQC160-10N excels as glue logic between microprocessors, memory, and peripherals. With 128 macrocells, designers can implement wait-state generators, interrupt arbiters, and chip-select decoding in a single 5V device. The 100 user I/Os comfortably handle 32-bit data buses plus control signals, and the deterministic 10 ns pin-to-pin delay ensures no metastability surprises. Compared to discrete 74-series TTL, the MAX 7000 reduces board area by 50-70% while remaining 5V-tolerant for direct connection to legacy microprocessors.
Recomendado
State Machine Control
The EPM7128SQC160-10N is ideal for implementing complex Moore/Mealy state machines in industrial controllers. Each macrocell contains a programmable flip-flop, allowing 128 independent state registers, while the global interconnect matrix (PIA) routes control signals with deterministic 10 ns delays. The 175.4 MHz counter frequency supports high-speed sequencing, and the non-volatile EEPROM fabric means state machines power up in a known condition - critical for safety interlocks where an SRAM-based FPGA might initialize unpredictably.
Recomendado
Industrial Control & 5V System Prototyping
The EPM7128SQC160-10N is widely used in industrial controllers and 5V system prototyping where its -40C to +85C industrial temperature range and 5V tolerance are mandatory. It handles timing-critical functions such as PWM generation, quadrature decoding, and serial-protocol bridging (RS-232/485) without needing level shifters. Designers can iterate logic via JTAG without removing the chip from the board, and the 10 ns pin-to-pin delay provides margin for cable-driver skew compensation.
Recomendado
Legacy System Upgrades & Drop-In Modernization
The EPM7128SQC160-10N serves as a drop-in modernization path for end-of-life 5V discrete logic boards. Designers can replace dozens of 74LS/74FTTL packages with one MAX 7000 part while retaining the 5V interface to upstream microprocessors. The 160-pin PQFP footprint is compatible with existing PCB layouts, and the JTAG programming chain allows rapid firmware updates without hardware rework - particularly valuable in aerospace and military retrofit programs.
Recomendado
Telecom Backplane Glue Logic
The EPM7128SQC160-10N is deployed in telecom backplanes for clock distribution, bus arbitration, and protocol bridging between legacy TDM buses and newer packet fabrics. Its 100 user I/Os comfortably handle 32-bit parallel buses plus JTAG and global clock/clear signals, while 128 macrocells implement multi-channel state machines in a single device. The non-volatile EEPROM fabric is especially valuable in central-office environments where power-cycles must result in deterministic, instant-on behavior.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM7128SQC160-10N — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM7128SQC160-10 | EPM7128SQC160-10YY | EPM7128SQC160-10ES | EPM7128SQC160-10F | EPM7128SQI160-10N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 100 | 100 | 100 | 100 | 100 | 100 |
| Pin-to-Pin Delay | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Counter Frequency | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz | 175.4 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial, lead-free) | -40C to +85C (engineering sample) | -40C to +85C (industrial, lead-free) | -40C to +85C (industrial) |
| RoHS Compliant | No (legacy SnPb) | No (legacy SnPb) | Yes (lead-free) | No (engineering sample) | Yes (lead-free) | No (legacy SnPb) |
Principais diferenciais
- Industrial temperature grade at the standard 10 ns speed (vs EPM7128SQC160-10)
- Non-volatile EEPROM fabric - instant deterministic boot (vs EPM7128AEFC100-10 (MAX 7000A))
- Higher logic density (128 macrocells) in the same MAX 7000 family (vs EPM7128SLC84-10)
Notas de projeto
Estimated: at 100 MHz toggle on 32 outputs at 5V, ICC is approximately 200 mA typical and can rise to 400 mA worst-case during simultaneous switching. Place 0.1 uF + 10 uF decoupling caps adjacent to each of the four VCC pins (104, 118, 148, plus pad 1) and four GND pins (10, 21, 32, plus pad 44) to keep the global interconnect matrix quiet. The MAX 7000 is a 5V-only family - do not apply 3.3V signals directly to user I/O; use external level shifters if interfacing to modern 3.3V logic.
Route JTAG signals (TCK/TDI/TMS/TDO) in a single daisy-chain with 10K pull-ups on TCK, TDI, TMS for proper boundary-scan operation per IEEE 1149.1. Place the EPM7128SQC160-10N away from switching power converters; the PQFP-160 lead pitch is 0.5 mm, so keep high-speed traces on inner layers with a continuous ground plane on layer 2 for controlled impedance and EMI suppression.
Do not confuse the EPM7128SQC160-10N (160-pin PQFP) with the EPM7128SQC100-10N (100-pin PQFP) or the EPM7128SLC84-10 (84-pin PLCC) - these are NOT pin-compatible despite the similar prefix. When migrating from older EPM7032/EPM7064 designs, re-validate the JTAG chain order because the -10N has a different boundary-scan ID than the smaller MAX 7000 variants. For new designs in 2026, prefer the MAX II EPM570 for 3.3V core voltages.
Informações de conformidade
EPM7128SQC160-10N is the legacy SnPb (non-lead-free) variant. Choose EPM7128SQC160-10F or EPM7128SQC160-10YY for RoHS-compliant designs. AEC-Q100 is not applicable (CPLD is not an automotive-qualified part); MAX 7000 family is not formally AEC-Q100 qualified. No REACH/CFMI statements in retrieved data.
