EPM9560RC208-4C - MAX 9000 CPLD 560 Macrocell | Altera
部品番号: EPM9560RC208-4C ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM9560RC208-4C 概要
A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of an FPGA with the non-volatile, instant-on characteristics of a PAL/PLD. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic device. MAX 9000 devices use EEPROM configuration cells, so they retain their design after power-down and require no external configuration memory, unlike SRAM-based FPGAs.
The EPM9560RC208-4C provides 560 macrocells organized into 12 logic array blocks (LABs), with 12,000 usable gates and 164 maximum user I/O pins. The -4 speed grade delivers 12 ns pin-to-pin logic delays and supports system clock frequencies up to 125 MHz. The 208-pin RQFP package offers a high I/O-to-package ratio for dense board-level glue logic, bus interfacing, and state machine implementations.
MAX 9000 devices are built on an EEPROM process that provides in-system programmability (ISP) via the JTAG interface, allowing field upgrades without removing the device from the board. The architecture uses a programmable interconnect array (PIA) to route signals between LABs, giving deterministic timing that simplifies worst-case timing analysis compared with segmented FPGA routing.
Typical applications include PCI bus bridging, DSP/processor glue logic, memory controllers, industrial control state machines, and legacy system replacement where instant-on operation and 5 V compatibility are required. The 5 V core also allows direct interfacing with TTL and 5 V CMOS logic without level shifters.
When designing with the EPM9560RC208-4C, note that it is a mature/legacy device; Altera (now Intel) has issued discontinuance notices for selected MAX 9000 ordering codes, and the 208-pin CQFP package has been replaced by the form-fit-functionally equivalent 208-pin RQFP. Verify availability and consider the RQFP variant for new designs.
This page synthesizes distributor availability, drop-in ordering-code alternatives, and practical design notes for the EPM9560RC208-4C that are not consolidated in the manufacturer datasheet, helping engineers evaluate replacement and sourcing options quickly.
ドロップイン代替品: EPM9560RC208-4C — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC208-4C （同一形状・フットプリント） — 相違点: Device Type, Speed Grade, Package, Pin-to-Pin Delay (tPD), Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC208-4
✅ ドロップイン✓ 在庫あり
$62 / 個
データシートを見る →EPM9560RC208-3
✅ ドロップイン✓ 在庫あり
$58.5 / 個
データシートを見る →EPM9560RC208-20
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-20C
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-15
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-10
✅ ドロップイン✓ 在庫あり
$15.4 / 個
データシートを見る →EPM9560RC208-4C 最大定格＆電気的特性
| Device Family | MAX 9000 (EPM9560) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 12 |
| Maximum User I/O Pins | 164 |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -4 (12 ns pin-to-pin) |
| 電源電圧 | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG ISP) |
| 動作温度範囲 | 0C to +70C (commercial) |
| 実装タイプ | Surface Mount |
| Pin-to-Pin Delay | 12 ns |
| Maximum System Frequency | 125 MHz |
| Manufacturer | Altera Corporation |
EPM9560RC208-4C 208-pin rqfp (power quad flat pack) ピン配置ガイド
EPM9560RC208-4C (208-pin rqfp (power quad flat pack) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560RC208-4C.
詳細は データシート をご参照ください。
主な用途
EPM9560RC208-4C の用途: 6 件s: PCI Bus Bridging and Interface Logic, Industrial Control State Machines, Legacy System Replacement and Obsolescence Management, DSP and Processor Glue Logic, Memory Controller and Address Decoding, Test and Measurement Instrumentation Logic.
PCI Bus Bridging and Interface Logic
The EPM9560RC208-4C fits PCI bus bridging because its 560 macrocells and 164 user I/O pins can implement the address/data multiplexing, parity generation, and target/source state machines required by a 32-bit 33 MHz PCI interface. The -4 speed grade's 12 ns pin-to-pin delay supports the 30 ns PCI setup/hold windows with margin, and the 5.0 V supply matches legacy 5 V PCI signaling directly. Designers typically place the CPLD between the host bus and a peripheral controller, using the EEPROM non-volatile configuration so the bridge is active immediately at power-up without a configuration PROM. The trade-off is higher static power than a modern 3.3 V CPLD, but no level shifters are needed.
おすすめ
Industrial Control State Machines
The EPM9560RC208-4C suits industrial control state machines because its 560 macrocells can implement multiple concurrent finite state machines, timers, and handshake logic on one device, replacing dozens of discrete 74-series ICs. The EEPROM configuration is non-volatile, so the controller boots deterministically in microseconds after power-up, which is critical for machine-safety interlocks that cannot wait for an SRAM FPGA to load. The 5.0 V I/O interfaces directly with legacy 24 V industrial I/O through optocouplers and drivers, and the 0C to +70C commercial range covers controlled-cabinet environments. The 12 ns pin-to-pin delay keeps interlock response times well under 1 microsecond.
おすすめ
Legacy System Replacement and Obsolescence Management
The EPM9560RC208-4C is frequently used to keep legacy systems running after the original glue-logic boards are discontinued. Because it is a 5.0 V EEPROM CPLD, it can absorb the function of obsolete PALs, GALs, and discrete TTL while preserving the original 5 V signal levels and timing. Altera's discontinuance notice states that EPM9560 devices in the 208-pin RQFP are form, fit and functionally equivalent to the discontinued 208-pin CQFP package, so existing CQFP designs can migrate to the RQFP footprint with a board revision. Engineers should qualify a second ordering code (for example EPM9560RC208-4) to reduce single-source risk.
おすすめ
DSP and Processor Glue Logic
The EPM9560RC208-4C provides glue logic around DSPs and legacy processors, implementing chip-select decoding, wait-state generation, interrupt prioritization, and bus-width adaptation. With 560 macrocells and 164 user I/O, it can decode multiple peripheral address ranges and generate the required control strobes without external decoders. The 12 ns pin-to-pin delay of the -4 grade keeps address-decode paths short enough for zero-wait-state operation at typical DSP bus speeds, and the 5.0 V supply matches older DSP I/O rails. The non-volatile EEPROM configuration means the glue logic is present before the processor releases reset, avoiding boot-order hazards common with SRAM-based programmable logic.
おすすめ
Memory Controller and Address Decoding
The EPM9560RC208-4C can implement SRAM, EPROM, and FIFO controllers where a discrete memory controller is unavailable or too inflexible. Its 560 macrocells hold the address multiplexers, refresh or wait-state counters, and chip-select decoders for multi-bank memory arrays, while the 164 user I/O pins connect directly to address, data, and control buses. The -4 speed grade's 12 ns pin-to-pin delay supports fast page-mode accesses, and the 5.0 V I/O matches legacy memory devices. Because configuration is stored in EEPROM, the controller is active immediately after power-up, which prevents the memory bus from floating during processor boot and avoids the need for external bus-hold logic.
おすすめ
Test and Measurement Instrumentation Logic
The EPM9560RC208-4C is used in test and measurement instruments for trigger logic, counter/timer arrays, and pattern generation. The 560 macrocells allow multiple independent counters and comparators to run concurrently, while the deterministic PIA interconnect gives predictable timing that simplifies calibration and worst-case analysis. The -4 speed grade's 12 ns pin-to-pin delay supports event detection in the tens-of-megahertz range, adequate for bench instruments and ATE interface boards. The 5.0 V supply and 0C to +70C commercial range suit rack-mounted equipment, and the non-volatile EEPROM configuration means the instrument is ready to measure immediately at power-on without a configuration load sequence.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC208-4C — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC208-4 | EPM9560RC208-3 | EPM9560RC208-20 | EPM9560RC208-15 |
|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Speed Grade | -4 (12 ns pin-to-pin) | -4 (12 ns) | -3 (approx. 10 ns) | -20 (20 ns) | -15 (15 ns) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Maximum User I/O | 164 | 164 | 164 | 164 | 164 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Faster -4 speed grade than -20 and -15 ordering codes （vs EPM9560RC208-20)
- Non-volatile EEPROM configuration （vs EPM9560RC208-4)
- Higher timing margin than -15 grade （vs EPM9560RC208-15)
設計ノート
The EPM9560RC208-4C requires a stable 5.0 V supply. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus at least one 10 uF bulk capacitor per device. Because MAX 9000 devices are EEPROM-based, they draw inrush current during power-up; ensure the regulator can supply the transient without dropping below the minimum operating voltage, or the device may fail to initialize.
The 208-pin RQFP package requires careful land-pattern design. Follow the Altera Package Information Datasheet for Mature Altera Devices for the recommended RQFP footprint, including the exposed thermal/ground pad. Use a ground plane under the device and connect all ground pins with short, low-inductance traces. For legacy CQFP-to-RQFP migration, note that the RQFP footprint differs from the CQFP footprint, so a board revision is required even though the devices are form, fit and functionally equivalent.
Do not assume the EPM9560RC208-4C is available in volume: Altera issued a product discontinuance notice for selected MAX 9000 ordering codes, and the part is obsolete. Qualify at least one alternate ordering code (for example EPM9560RC208-4 or EPM9560RC208-3) and verify live distributor stock before committing to production. Also confirm the JTAG ISP chain is correctly terminated, since an unterminated TCK/TMS path can prevent in-system programming.
コンプライアンス情報
Compliance data was not present in the verified web data for EPM9560RC208-4C. The device is a mature/obsolete MAX 9000 part; confirm RoHS/REACH status with the distributor or manufacturer before use in regulated markets.