EPM9560RC208-4 - MAX 9000 CPLD 560 Macrocells | Altera
MPN: EPM9560RC208-4 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88 | $880.00 |
| 100 | $78 | $7,800.00 |
| 500 | $70 | $35,000.00 |
| 1,000 | $62 | $62,000.00 |
Drop-in alternatives for EPM9560RC208-4 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-3
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$58.5 / Unit
View Datasheet βEPM9560RC208-10
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$15.4 / Unit
View Datasheet βEPM9560RC208-15
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View Datasheet βEPM9560RC208-20
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View Datasheet βEPM9560RC208-4 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device | EPM9560 |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Maximum Operating Frequency | 118.3 MHz |
| Pin-to-Pin Delay (tPD) | 4 ns |
| Speed Grade | -4 |
| Supply Voltage (VCC) | 5 V |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 96 (approx., 208-pin RQFP) |
| Dedicated Inputs | 16 |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| Configuration Memory | EEPROM (non-volatile) |
| MultiVolt I/O | 5.0 V / 3.3 V / 2.5 V |
| Operating Temperature | 0C to +70C (commercial) |
EPM9560RC208-4 Pin Configuration
| Pin 1 | I/O β User I/O pin (LAB bank) |
| Pin 2 | I/O β User I/O pin (LAB bank) |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β User I/O pin (LAB bank) |
| Pin 5 | I/O β User I/O pin (LAB bank) |
| Pin 6 | VCC β 5 V supply |
| Pin 7 | I/O β User I/O pin (LAB bank) |
| Pin 8 | I/O β User I/O pin (LAB bank) |
| Pin 9 | I/O β User I/O pin (LAB bank) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O pin (LAB bank) |
| Pin 12 | I/O β User I/O pin (LAB bank) |
| Pin 13 | I/O β User I/O pin (LAB bank) |
| Pin 14 | VCC β 5 V supply |
| Pin 15 | I/O β User I/O pin (LAB bank) |
| Pin 16 | I/O β User I/O pin (LAB bank) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin (LAB bank) |
| Pin 19 | I/O β User I/O pin (LAB bank) |
| Pin 20 | I/O β User I/O pin (LAB bank) |
| Pin 21 | VCC β 5 V supply |
| Pin 22 | I/O β User I/O pin (LAB bank) |
| Pin 23 | I/O β User I/O pin (LAB bank) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin (LAB bank) |
| Pin 26 | I/O β User I/O pin (LAB bank) |
| Pin 27 | I/O β User I/O pin (LAB bank) |
| Pin 28 | VCC β 5 V supply |
| Pin 29 | I/O β User I/O pin (LAB bank) |
| Pin 30 | I/O β User I/O pin (LAB bank) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (LAB bank) |
| Pin 33 | I/O β User I/O pin (LAB bank) |
| Pin 34 | I/O β User I/O pin (LAB bank) |
| Pin 35 | VCC β 5 V supply |
| Pin 36 | I/O β User I/O pin (LAB bank) |
| Pin 37 | I/O β User I/O pin (LAB bank) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin (LAB bank) |
| Pin 40 | I/O β User I/O pin (LAB bank) |
| Pin 41 | I/O β User I/O pin (LAB bank) |
| Pin 42 | VCC β 5 V supply |
| Pin 43 | I/O β User I/O pin (LAB bank) |
| Pin 44 | I/O β User I/O pin (LAB bank) |
| Pin 45 | GND β Ground |
| Pin 46 | I/O β User I/O pin (LAB bank) |
| Pin 47 | I/O β User I/O pin (LAB bank) |
| Pin 48 | I/O β User I/O pin (LAB bank) |
| Pin 49 | VCC β 5 V supply |
| Pin 50 | I/O β User I/O pin (LAB bank) |
| Pin 51 | I/O β User I/O pin (LAB bank) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O pin (LAB bank) |
| Pin 54 | I/O β User I/O pin (LAB bank) |
| Pin 55 | I/O β User I/O pin (LAB bank) |
| Pin 56 | VCC β 5 V supply |
| Pin 57 | I/O β User I/O pin (LAB bank) |
| Pin 58 | I/O β User I/O pin (LAB bank) |
| Pin 59 | GND β Ground |
| Pin 60 | I/O β User I/O pin (LAB bank) |
| Pin 61 | I/O β User I/O pin (LAB bank) |
| Pin 62 | I/O β User I/O pin (LAB bank) |
| Pin 63 | VCC β 5 V supply |
| Pin 64 | I/O β User I/O pin (LAB bank) |
| Pin 65 | I/O β User I/O pin (LAB bank) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O pin (LAB bank) |
| Pin 68 | I/O β User I/O pin (LAB bank) |
| Pin 69 | I/O β User I/O pin (LAB bank) |
| Pin 70 | VCC β 5 V supply |
| Pin 71 | I/O β User I/O pin (LAB bank) |
| Pin 72 | I/O β User I/O pin (LAB bank) |
| Pin 73 | GND β Ground |
| Pin 74 | I/O β User I/O pin (LAB bank) |
| Pin 75 | I/O β User I/O pin (LAB bank) |
| Pin 76 | I/O β User I/O pin (LAB bank) |
| Pin 77 | VCC β 5 V supply |
| Pin 78 | I/O β User I/O pin (LAB bank) |
| Pin 79 | I/O β User I/O pin (LAB bank) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin (LAB bank) |
| Pin 82 | I/O β User I/O pin (LAB bank) |
| Pin 83 | I/O β User I/O pin (LAB bank) |
| Pin 84 | VCC β 5 V supply |
| Pin 85 | I/O β User I/O pin (LAB bank) |
| Pin 86 | I/O β User I/O pin (LAB bank) |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O pin (LAB bank) |
| Pin 89 | I/O β User I/O pin (LAB bank) |
| Pin 90 | I/O β User I/O pin (LAB bank) |
| Pin 91 | VCC β 5 V supply |
| Pin 92 | I/O β User I/O pin (LAB bank) |
| Pin 93 | I/O β User I/O pin (LAB bank) |
| Pin 94 | GND β Ground |
| Pin 95 | I/O β User I/O pin (LAB bank) |
| Pin 96 | I/O β User I/O pin (LAB bank) |
| Pin 97 | I/O β User I/O pin (LAB bank) |
| Pin 98 | VCC β 5 V supply |
| Pin 99 | I/O β User I/O pin (LAB bank) |
| Pin 100 | I/O β User I/O pin (LAB bank) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (LAB bank) |
| Pin 103 | I/O β User I/O pin (LAB bank) |
| Pin 104 | I/O β User I/O pin (LAB bank) |
| Pin 105 | VCC β 5 V supply |
| Pin 106 | I/O β User I/O pin (LAB bank) |
| Pin 107 | I/O β User I/O pin (LAB bank) |
| Pin 108 | GND β Ground |
| Pin 109 | I/O β User I/O pin (LAB bank) |
| Pin 110 | I/O β User I/O pin (LAB bank) |
| Pin 111 | I/O β User I/O pin (LAB bank) |
| Pin 112 | VCC β 5 V supply |
| Pin 113 | I/O β User I/O pin (LAB bank) |
| Pin 114 | I/O β User I/O pin (LAB bank) |
| Pin 115 | GND β Ground |
| Pin 116 | I/O β User I/O pin (LAB bank) |
| Pin 117 | I/O β User I/O pin (LAB bank) |
| Pin 118 | I/O β User I/O pin (LAB bank) |
| Pin 119 | VCC β 5 V supply |
| Pin 120 | I/O β User I/O pin (LAB bank) |
| Pin 121 | I/O β User I/O pin (LAB bank) |
| Pin 122 | GND β Ground |
| Pin 123 | I/O β User I/O pin (LAB bank) |
| Pin 124 | I/O β User I/O pin (LAB bank) |
| Pin 125 | I/O β User I/O pin (LAB bank) |
| Pin 126 | VCC β 5 V supply |
| Pin 127 | I/O β User I/O pin (LAB bank) |
| Pin 128 | I/O β User I/O pin (LAB bank) |
| Pin 129 | GND β Ground |
| Pin 130 | I/O β User I/O pin (LAB bank) |
| Pin 131 | I/O β User I/O pin (LAB bank) |
| Pin 132 | I/O β User I/O pin (LAB bank) |
| Pin 133 | VCC β 5 V supply |
| Pin 134 | I/O β User I/O pin (LAB bank) |
| Pin 135 | I/O β User I/O pin (LAB bank) |
| Pin 136 | GND β Ground |
| Pin 137 | I/O β User I/O pin (LAB bank) |
| Pin 138 | I/O β User I/O pin (LAB bank) |
| Pin 139 | I/O β User I/O pin (LAB bank) |
| Pin 140 | VCC β 5 V supply |
| Pin 141 | I/O β User I/O pin (LAB bank) |
| Pin 142 | I/O β User I/O pin (LAB bank) |
| Pin 143 | GND β Ground |
| Pin 144 | I/O β User I/O pin (LAB bank) |
| Pin 145 | I/O β User I/O pin (LAB bank) |
| Pin 146 | I/O β User I/O pin (LAB bank) |
| Pin 147 | VCC β 5 V supply |
| Pin 148 | I/O β User I/O pin (LAB bank) |
| Pin 149 | I/O β User I/O pin (LAB bank) |
| Pin 150 | GND β Ground |
| Pin 151 | I/O β User I/O pin (LAB bank) |
| Pin 152 | I/O β User I/O pin (LAB bank) |
| Pin 153 | I/O β User I/O pin (LAB bank) |
| Pin 154 | VCC β 5 V supply |
| Pin 155 | I/O β User I/O pin (LAB bank) |
| Pin 156 | I/O β User I/O pin (LAB bank) |
| Pin 157 | GND β Ground |
| Pin 158 | I/O β User I/O pin (LAB bank) |
| Pin 159 | I/O β User I/O pin (LAB bank) |
| Pin 160 | I/O β User I/O pin (LAB bank) |
| Pin 161 | VCC β 5 V supply |
| Pin 162 | I/O β User I/O pin (LAB bank) |
| Pin 163 | I/O β User I/O pin (LAB bank) |
| Pin 164 | GND β Ground |
| Pin 165 | I/O β User I/O pin (LAB bank) |
| Pin 166 | I/O β User I/O pin (LAB bank) |
| Pin 167 | I/O β User I/O pin (LAB bank) |
| Pin 168 | VCC β 5 V supply |
| Pin 169 | I/O β User I/O pin (LAB bank) |
| Pin 170 | I/O β User I/O pin (LAB bank) |
| Pin 171 | GND β Ground |
| Pin 172 | I/O β User I/O pin (LAB bank) |
| Pin 173 | I/O β User I/O pin (LAB bank) |
| Pin 174 | I/O β User I/O pin (LAB bank) |
| Pin 175 | VCC β 5 V supply |
| Pin 176 | TDI β JTAG Test Data In |
| Pin 177 | TMS β JTAG Test Mode Select |
| Pin 178 | TCK β JTAG Test Clock |
| Pin 179 | TDO β JTAG Test Data Out |
| Pin 180 | I/O β User I/O pin (LAB bank) |
| Pin 181 | GND β Ground |
| Pin 182 | I/O β User I/O pin (LAB bank) |
| Pin 183 | I/O β User I/O pin (LAB bank) |
| Pin 184 | VCC β 5 V supply |
| Pin 185 | INPUT/GCLK1 β Dedicated input / global clock 1 |
| Pin 186 | INPUT/GCLK2 β Dedicated input / global clock 2 |
| Pin 187 | INPUT/GCLK3 β Dedicated input / global clock 3 |
| Pin 188 | INPUT/GCLK4 β Dedicated input / global clock 4 |
| Pin 189 | INPUT/OE1 β Dedicated input / global OE 1 |
| Pin 190 | INPUT/OE2 β Dedicated input / global OE 2 |
| Pin 191 | INPUT/CLR β Dedicated input / global clear |
| Pin 192 | INPUT β Dedicated input |
| Pin 193 | GND β Ground |
| Pin 194 | INPUT β Dedicated input |
| Pin 195 | INPUT β Dedicated input |
| Pin 196 | INPUT β Dedicated input |
| Pin 197 | VCC β 5 V supply |
| Pin 198 | INPUT β Dedicated input |
| Pin 199 | INPUT β Dedicated input |
| Pin 200 | INPUT β Dedicated input |
| Pin 201 | INPUT β Dedicated input |
| Pin 202 | GND β Ground |
| Pin 203 | INPUT β Dedicated input |
| Pin 204 | INPUT β Dedicated input |
| Pin 205 | INPUT β Dedicated input |
| Pin 206 | VCC β 5 V supply |
| Pin 207 | INPUT β Dedicated input |
| Pin 208 | INPUT β Dedicated input |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-4 is suitable for 6 applications: PCI Bus Interface Bridging, High-Speed Address Decoding, Telecom Backplane Glue Logic, Industrial Automation Control Logic, Legacy Peripheral Chip Consolidation, Memory and DSP Interface Bridging.
PCI Bus Interface Bridging
The EPM9560RC208-4 is well suited for PCI bus interface bridging because its 560 macrocells and 4 ns tPD enable single-cycle address and command decoding across 32-bit PCI buses. In a typical 5 V PCI design, the device decodes C/BE and address lines while generating chip-selects for memory and peripheral devices, replacing multiple discrete 74FCT and PAL devices with one non-volatile part. The 16 dedicated inputs handle PCI clock and control signals with predictable timing, while the MultiVolt I/O simplifies bridging to 3.3 V downstream peripherals. The 4 ns grade ensures timing margin under worst-case load and temperature conditions.
Recommended
High-Speed Address Decoding
For high-speed microprocessor address decoding, the EPM9560RC208-4's 560 macrocells support large memory maps with multiple chip-select outputs. A typical 32-bit address decoder needs 8 to 16 product terms per chip-select; the EPM9560's 16 LABs with 16 macrocells each provide ample capacity for 12 to 24 chip-select outputs plus address-strobe gating logic. The 4 ns tPD ensures the chip-select signals arrive within the same clock cycle as the address latch, which is critical at 50 MHz and above. The non-volatile EEPROM configuration means no boot PROM is required and the design is ready at power-on.
Recommended
Telecom Backplane Glue Logic
In telecom backplane designs, the EPM9560RC208-4 consolidates bus arbitration, interrupt steering, and reset distribution across multiple line cards. The 208-pin RQFP package provides sufficient I/O for 96 user I/O plus 16 dedicated inputs to handle bus control signals, JTAG chain management, and inter-card communication. The MultiVolt I/O allows the device to interface between 5 V legacy cards and 3.3 V ASICs without external level shifters. The non-volatile configuration supports instant-on operation required for telecom hot-swap and redundancy architectures.
Recommended
Industrial Automation Control Logic
The EPM9560RC208-4 is used in industrial PLC and motor-control designs to consolidate ladder-logic-equivalent state machines, encoder-decoder logic, and safety-interlock gating. Its deterministic 4 ns tPD enables precise timing for PWM generation and servo-loop control, while the EEPROM-based configuration survives industrial EMI events that would corrupt SRAM-based devices. The 208-pin RQFP supports the I/O count required for multi-axis control with parallel encoder, limit-switch, and contactor interfaces. Designers often use the JTAG interface for in-system programming during commissioning.
Recommended
Legacy Peripheral Chip Consolidation
Designers use the EPM9560RC208-4 to replace multiple 22V10, 26V12, and discrete TTL/CMOS glue-logic devices in legacy designs with a single programmable part. This consolidation reduces PCB area, simplifies inventory, and improves reliability by removing dozens of solder joints. The 12,000 usable gates and 560 macrocells provide enough capacity to absorb entire schematics pages of discrete logic. The 5 V VCC and TTL-compatible I/O match the legacy signal environment, eliminating the need for voltage-translation buffers in retrofit applications.
Recommended
Memory and DSP Interface Bridging
The EPM9560RC208-4 bridges asynchronous SRAM, Flash, and DSP peripherals to microprocessors with deterministic timing. The 4 ns tPD enables zero-wait-state interfacing at 40 MHz bus speeds, while the 560 macrocells can implement bank-switch logic, byte-lane steering, and parity/ECC handling for 32-bit memory subsystems. The device's MultiVolt I/O supports 5 V, 3.3 V, and 2.5 V signaling, simplifying designs that mix legacy and modern DSPs. The JTAG interface enables in-system programming and boundary-scan test for high-reliability applications.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-4 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-3 | EPM9560RC208-10 | EPM9560RC208-15 | EPM9560RC208-20 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 4 ns | 3 ns (-25%) | 10 ns (+150%) | 15 ns (+275%) | 20 ns (+400%) |
| Maximum Frequency (fMAX) | 118.3 MHz | 147 MHz | 71.4 MHz | 50 MHz | 38.5 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lowest propagation delay in the discontinued EPM9560 family (vs EPM9560RC208-20)
- Same 208-pin RQFP footprint as other EPM9560RC208 grades (vs EPM9560RC208-3)
- Non-volatile EEPROM configuration eliminates boot PROM (vs SRAM-based FPGAs)
Design Notes
The EPM9560RC208-4 operates from a 5 V VCC supply with multiple VCC and GND pins distributed around the 208-pin RQFP package for power integrity. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close as possible to the package, and add a bulk 10 to 47 uF tantalum or aluminum electrolytic capacitor near the device. The MultiVolt I/O pins draw power from VCCIO rails, which can be set independently to 5.0 V, 3.3 V, or 2.5 V; ensure each VCCIO bank is properly decoupled to prevent logic errors during I/O switching.
Do not use the EPM9560RC208-4 in new designs: the MAX 9000 family is obsolete and Intel/Altera recommends migrating to MAX II, MAX V, or MAX 10 CPLDs. For legacy board repair or form-fit-function replacement, verify exact speed-grade compatibility because the -4 has tighter timing than the more available -20 grade. Also note that the original 208-pin ceramic CQFP was discontinued; only the 208-pin RQFP package remains form-fit-function equivalent, so legacy CQFP boards must be respun for RQFP footprints.
The EPM9560RC208-4's deterministic 4 ns tPD and PIA-based interconnect give predictable timing, but simultaneous switching of multiple I/O pins can cause ground bounce on shared GND pins. Use a 4-layer PCB with dedicated ground and power planes, and place series resistors (22 to 33 ohm) on high-speed outputs to dampen reflections. The MultiVolt I/O banks must not be mixed across voltage domains on the same physical bank; assign each bank to a single VCCIO voltage to prevent contention.
Compliance Information
Compliance status not provided in Verified Web Data. EPM9560 family was originally specified before RoHS mandates; later production runs may have transitioned to lead-free but specific compliance is not confirmed in the available data.
